Forming planarized semiconductor structures
OwnerDaniel Xu, Tyler Lowrey +4inventors
InventorsDaniel Xu, Tyler Lowrey, Jong-Won Lee, Kyu Min, Donghui Lu, Jenn Chow
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Abstract
A planarized surface may be formed by initially forming an aperture through an insulating layer. The insulating layer and its aperture may be conformally coated with a conductive material that ultimately acts as a planarization stop. The conductive material may then be covered with another insulator that fills the remainder of the aperture. Thereafter, the structure may be planarized down to the conductive layer that acts as a planarization stop.
Claims33
A method comprising:
- chemical mechanical polishing through a portion of an insulating third layer down to a conductive second layer coated on a first layer having an opening filled at least in part by said third layer.
A semiconductor structure comprising:
- a dielectric material formed over a substrate, said dielectric material having an aperture formed at least partially through said dielectric material;
- a conductive material conformally coated over said dielectric and said aperture;
- and
- a thermally insulating material formed within said aperture over said conductive material.
A method comprising:
- chemical mechanical polishing through a portion of a thermally insulating third layer down to a conductive layer coated on a first layer having an opening filled at least in part with said third layer;
- forming a pair of spaced electrodes so that one of said electrodes is coupled to said conductive layer;
- and
- forming a memory material between said electrodes.
A memory comprising:
- an electrical contact coupled to a line in a substrate;
- a tubular conductor extending upwardly from said contact, said tubular conductor being filled with a thermally insulating material;
- a lower electrode coupled to said tubular electrode;
- a memory material over said lower electrode;
- and
- an upper electrode over said memory material.
A system comprising:
- a processor-based device;
- a wireless interface coupled to said processor-based device;
- and
- a semiconductor memory coupled to said device, said memory including a substrate, said substrate including a conductive line, a contact formed over said substrate electrically coupled to said conductive line, and a memory element over said contact, said memory element coupled to said contact by a tubular conductor filled with a thermally insulating material.
Dependencies are inferred from the claim text.