Method and circuit for determining the response curve knee point in active pixel image sensors with extended dynamic range

A pixel circuit, comprising:

• a photo sensor;
• a storage node for receiving charges from said photo sensor;
• and
• a reset transistor for resetting said storage node, said reset transistor being switchably coupled to a first and second voltage level.

An image array pixel comprising:

• a change storing node;
• a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to a first and second voltage, the other of said source/drain regions being coupled to said node;
• and
• a source-follower transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions of said source-follower transistor being coupled to said first and second voltage and to said one of said source/drain regions of said reset transistor.

An image array comprising:

• a pixel cell;
• a power supply circuit for selectively providing a first and second reset voltage;
• and
• a switch circuit for coupling said power supply circuit to a storage node of said pixel cell.

A method of operating pixel of pixel array, said method comprising:

• flooding a pixel in said array to clear any stored signal;
• applying a first reset voltage to said charge storage area of said pixel;
• sampling a first voltage signal from said charge storage area;
• applying a second reset voltage to said charge storage area;
• sampling a second voltage signal from said charge storage area;
• and
• determining a difference between said first and second sampled voltage signals.

A method of determining the intermediate reset voltage of an image array, said method comprising:

• sampling and storing a first set of integrated signals from an array of pixels;
• applying a first reset voltage to said array of pixels;
• sampling and storing a first set of reset signals from said array of pixels;
• applying a second reset voltage to said array of pixels;
• sampling and storing a second set of integrated signals from said array of pixels;
• applying said first reset voltage to said array of pixels;
• sampling and storing a second set of reset signals from said array of pixels;
• and
• determining a difference between said first set and second set of sampled voltage signals.

A processing system, comprising:

• a processor;
• an imager array coupled to said processor, one pixel of said image array comprising:
• a charge sharing node;
• and
• a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to a first and second voltage, the other of said source/drain regions being coupled to said node.

A processor system, comprising:

• a processor;
• an imager array coupled to said processor, one pixel of said imager array comprising:
• a pixel cell;
• a power supply circuit for reflectively providing a first and second reset voltage;
• and
• a switch circuit for coupling said power supply circuit to a storage node of said pixel cell.

An imaging device, comprising:

• a processor;
• an imager array coupled to said processor, one pixel of said image array comprising:
• a charge sharing node;
• and
• a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to a first and second voltage, the other of said source/drain regions being coupled to said node.