Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof

A method of fabricating an interconnection structure in a semiconductor device comprising:

• forming a first active region in a substrate;
• forming a second active region in the substrate;
• forming a first field region in the substrate disposed between the first active region and the second active region;
• forming an interlayer dielectric on the substrate;
• forming a first opening in the interlayer dielectric exposing the first active region and the second active region;
• and
• filling the first opening with a conductive material to form a first unitary interconnection structure connecting the first active region to the second active region.

A method of fabricating an interconnection structure in a semiconductor substrate comprising:

• forming a field area defining a first active region, a second active region, a third active region, and a fourth active region in a substrate:
• forming a gate insulator and a first conductive layer on a surface of the substrate;
• patterning the first conductive layer and the gate insulator to form a first conductive line and a second conductive line on field regions adjoining both sides of the third active region and to form a gate electrode and gate insulator on the fourth active region;
• forming heavily doped regions at the first active region, the second active region, the third active region, and the fourth active region using the field area and the gate electrode as an ion implantation mask;
• forming an interlayer dielectric on the surface of the substrate and on the first conductive line, the second conductive line, and the gate electrode;
• selectively etching the interlayer dielectric to form a first opening exposing the first active region and the second active region, a second opening exposing top surfaces of the first conductive line and the second conductive line, and a third opening exposing the fourth active region and a top surface of the gate electrode, wherein a portion of the interlayer dielectric remains in a gap between the first and the second conductive lines;
• and
• filling the first, second and third openings with a conductive material to form a first unitary interconnection structure connecting the first active region to the second active region, a second unitary interconnection structure connecting the first conductive line to the second conductive line, and a third unitary interconnection structure connecting the gate electrode to the fourth active region.