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AssigneeInfineon Technologies AG
InventorsThomas Bottner, Stefan Drexl, Thomas Huttner, Martin Seck
Estimating the term…
An explanation is given of, inter alia, an integrated circuit arrangement (100) containing an npn transistor (102) and a pnp transistor (104). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout (142) for an edge terminal region (120) and if the edge terminal region (120) has a part near the substrate which is arranged in the cutout (142) and a part remote from the substrate which is arranged outside the cutout (142) and overlaps the base terminal region (139).
An integrated circuit arrangement (100), having at least one npn transistor (104) containing, in the following order in a manner adjoining one another, an n-doped edge region (182), a p-doped base region (184) and a further n-doped edge region (186), and having at least one pnp transistor (102) containing, in the following order in a manner adjoining one another, a p-doped edge region (114), an n-doped base region (116) and a further p-doped edge region (186), the integrated circuit arrangement comprising
A method for fabricating an integrated circuit arrangement (100) which contains at least one npn transistor (102) containing, in the following order in a manner adjoining one another, an n-doped edge region (118), a p-doped base region (114) and a further n-doped edge region (118), and which contains at least one pnp transistor (104) containing, in the following order in a manner adjoining one another, a p-doped edge region (182), an n-doped base region (184) and a further p-doped edge region (186), the method comprising the following method acts, which are implemented without restrictions by the order prescribed:
Dependencies are inferred from the claim text.