Antifuse structure and method of use
AssigneeMicron Technology, Inc.
InventorsKenneth Marr, Shubneesh Batra
Life of this patent
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Abstract
An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programming voltage is coupled to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse. The first programming voltage may be coupled to an ohmic contact in the well in the antifuse.
Claims46
An electronic device comprising:
- a substrate;
- and
- an antifuse disposed on the substrate, the antifuse including:
- a body;
- a conductive terminal;
- an ohmic contact in the body, the ohmic contact accessible to an external pin;
- a insulator between the body and the conductive terminal.
An electronic device comprising:
- a substrate;
- and
- an antifuse disposed on the substrate, the antifuse including:
- a body isolated by an isolation insulator;
- an ohmic contact in the body, the ohmic contact accessible to an external pin;
- a conductive terminal;
- and
- a gate insulator between the body and the conductive terminal.
An integrated circuit comprising:
- a circuit;
- a plurality of antifuses, each antifuse including:
- a first conductive terminal of a first conductivity type coupled to the circuit to receive a first programming voltage;
- and
- a well of a second conductivity type in a substrate of the first conductivity type;
- an insulator between the body and the first conductive terminal;
- and
- a ohmic contact in the well;
- and
- an external pin in the integrated circuit coupled to the ohmic contact of each antifuse to receive a second programming voltage.
A memory comprising:
- an array of memory cells;
- and
- a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array;
- each antifuse including:
- a body;
- a conductive terminal;
- an ohmic contact in the body, the ohmic contact accessible to an external pin;
- and
- an insulator between the body and the conductive terminal.
A memory comprising:
- an array of memory cells;
- and
- a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array;
- each antifuse including:
- a first conductive terminal of a first conductivity type coupled to a read circuit to receive a first programming voltage;
- and
- a well of a second conductivity type in a substrate of the first conductivity type;
- an insulator between the body and the first conductive terminal;
- and
- a ohmic contact in the well;
- and
- an external pin in the memory coupled to the ohmic contact of each antifuse to receive a second programming voltage.
A memory comprising:
- an array of memory cells;
- and
- a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array;
- each antifuse including:
- body isolated by an isolation insulator;
- an ohmic contact in the body accessible to an external pin;
- a conductive terminal;
- and
- a gate insulator between the body and the conductive terminal.
A system comprising:
- a processor;
- a memory coupled to the processor, the memory including:
- an array of memory cells;
- and
- a number of antifuses disposed on a substrate to indicate locations of redundant memory cells in the array;
- each antifuse including:
- a body;
- a conductive terminal;
- an ohmic contact in the body, the ohmic contact accessible to an external pin;
- and
- an insulator between the body and the conductive terminal.
A memory device comprising:
- an array of memory cells;
- an address decoder;
- a plurality of input/output paths;
- an input/output control circuit;
- and
- an antifuse bank comprising:
- a programming logic circuit;
- an external pin;
- and
- a plurality of antifuses disposed on a substrate, each antifuse comprising:
- a well of a first conductivity type in the substrate of a second conductivity type, the well being coupled to the external pin by an ohmic contact in the well;
- a first conductive terminal of the second conductivity type coupled to the programming logic circuit;
- and
- an insulator between the well and the first conductive terminal.
Dependencies are inferred from the claim text.