Strained Si/SiGe/SOI islands and processes of making same

A process comprising:

• above a substrate, forming a strained silicon layer above a semiconductive silicon compound layer;
• forming a recess in the substrate to laterally isolate the strained silicon layer;
• and vertically isolating the strained silicon layer from the substrate by undercutting;
• wherein vertically isolating further includes:
• forming a spacer in the recess;
• and
• isotropically etching in the recess under conditions to undercut the spacer.

A process comprising:

• forming a relaxed SiGe layer above a substrate;
• forming a strained silicon layer above the relaxed SiGe layer;
• forming at least one recess in the substrate to laterally isolate the strained silicon layer;
• and
• vertically isolating the strained silicon layer from the substrate by undercutting.

A process comprising:

• forming a relaxed SiGe layer above a substrate;
• forming a strained silicon layer above the relaxed SiGe layer;
• forming at least one recess in the substrate to laterally isolate the strained silicon layer;
• and
• vertically isolating the strained silicon layer from the substrate by undercutting,
• wherein vertically isolating further includes:
• forming a spacer in the at least one recess;
• isotropically etching in the at least one recess under conditions to undercut the spacer;
• and
• forming an oxide in the substrate.

A process of forming an active area, comprising:

• forming a deep implantation in a substrate below a top surface of the substrate;
• forming a semiconductive silicon compound layer above the deep implantation;
• forming a strained silicon layer above the semiconductive silicon compound layer;
• forming a recess in the substrate to laterally isolate the strained silicon layer;
• and
• vertically isolating the strained silicon layer from the substrate by undercutting.

A process comprising:

• forming a recess in a substrate to form an active area precursor;
• partially undercutting the active area precursor;
• forming an oxide in the undercutting to fully undercut the active area precursor;
• forming a semiconductive silicon compound layer above and on the active area precursor;
• forming a strained silicon layer above and on the semiconductive silicon compound layer;
• and
• forming at least one junction in the strained silicon layer.

An article comprising:

• a substrate;
• a relaxed semiconductive silicon compound layer disposed above the substrate;
• a strained silicon layer disposed above the relaxed semiconductive silicon compound layer;
• wherein the strained silicon layer is laterally isolated by a shallow trench isolation, and wherein the strained silicon layer is vertically isolated by a thermal oxide.

An electrical device comprising:

• a substrate;
• a relaxed semiconductive silicon compound layer disposed above the substrate;
• a strained silicon layer disposed above the relaxed semiconductive silicon compound layer, wherein the strained silicon layer is laterally isolated by a shallow trench isolation, and wherein the strained silicon layer is vertically isolated by a thermal oxide;
• and
• a gate disposed above the strained silicon layer.

A method of assembling an electrical device comprising:

• above a substrate, forming a strained silicon layer above a semiconductive silicon compound layer;
• forming a recess in the substrate to laterally isolate the strained silicon layer;
• vertically isolating the strained silicon layer from the substrate by undercutting;
• and
• forming at least one junction in the strained silicon layer.

A computer system, comprising:

• a processor;
• a memory system coupled to the processor;
• an input/output (I/O) circuit coupled to the processor and the memory system;
• and
• a strained silicon on insulator structure disposed in the processor or the memory system, the strained silicon on insulator structure including:
• a substrate;
• a relaxed semiconductive silicon compound layer disposed above the substrate;
• a strained silicon layer disposed above the relaxed semiconductive silicon compound layer;
• wherein the strained silicon layer is laterally isolated by a shallow trench isolation, and wherein the strained silicon layer is vertically isolated by a dielectric.