Atomic layer deposited Zr-Sn-Ti-O films using TiI4

A capacitor, comprising:

• a first conductive layer on a substrate;
• a dielectric layer containing a Zr—Sn—Ti—O layer formed by atomic layer deposition using TiI4, the dielectric layer disposed on the first conductive layer;
• and
• a second conductive layer disposed on the dielectric layer.

A transistor comprising:

• a body region on a substrate between a source region and a drain region;
• a dielectric film containing a Zr—Sn—Ti—O layer formed by atomic layer deposition using TiI4, the dielectric film disposed on the body region between the source region and the drain region;
• and
• a gate coupled to the dielectric film.

A transistor comprising:

• a body region on a substrate between a source region and a drain region;
• a gate dielectric disposed on the body region;
• a floating gate disposed on the gate dielectric;
• a control gate;
• a floating gate dielectric interposed between the floating gate and the control gate, wherein at least one of the gate dielectric and the floating gate dielectric includes a dielectric film containing a Zr—Sn—Ti—O layer formed by atomic layer deposition using TiI4.

A memory comprising:

• a number of access transistors in an array on a substrate, each access transistor having a body region between a source region and a drain region, at least one access transistor including a gate coupled to a dielectric film disposed above the body region, the dielectric film containing a Zr—Sn—Ti—O layer formed by atomic layer deposition using TiI4;
• a number of word lines coupled to a number of the gates of the number of access transistors;
• a number of source lines coupled to a number of the source regions of the number of access transistors;
• and
• a number of bit lines coupled to a number of the drain regions of the number of access transistors.

An electronic system comprising:

• a processor;
• a system bus;
• and
• a memory coupled to the processor by the system bus, the memory including:
• a number of access transistors in an array on a substrate, each access transistor having a body region between a source region and a drain region, at least one access transistor including a gate coupled to a dielectric film disposed above the body region, the dielectric film containing a Zr—Sn—Ti—O layer formed by atomic layer deposition using TiI4;
• a number of word lines coupled to a number of the gates of the number of access transistors;
• a number of source lines coupled to a number of the source region of the number of access transistors;
• and
• a number of bit lines coupled to a number of the drain region of the number of access transistors.