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US 2004/0210809 A1Published application
Input/output compression test circuit
AssigneeHynix Semiconductor Inc.
InventorYong Deok Cho
Life of this patent
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Abstract
The I/O compression test circuit performs the test on the global I/O lines divided into groups when failure occurs, thereby improving the repair efficiency. Also, since the configuration of the test circuit is simplified by using a reset circuit, the delay time generated by a logic circuit device is reduced, thereby decreasing test time. Additionally, two sampling clock signals enable memory cells to perform a stable operation on skew between global I/O lines or glitch generated in internal circuits.
Claims11
An I/O compression test circuit for compression testing data loaded on a plurality of global I/O lines, comprising:
- a plurality of test blocks for testing a plurality of global I/O line groups depending on a test enable signal, wherein the plurality of global I/O lines are divided into the plurality of global I/O line groups;
- a decision block for deciding a test result in response to output signals from the plurality of test blocks;
- a driving block for outputting a test result signal in response to a decision signal outputted from the decision block;
- and
- a control block for controlling a test timing of the test blocks, initializing an input terminal of the decision block and controlling a driving timing of the driving block.
2 more elements
Dependencies are inferred from the claim text.