US 2004/0210780 A1Published application

Micro controller unit

AssigneeRenesas Technology Corp.

InventorsHiroki Takahashi, Kazuo Nakamura

Life of this patent

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Abstract

It is an object to increase a speed of a CPU operation irrespective of an operation speed of a peripheral circuit and to prevent an increase in power consumption from being thereby caused. A clock generating circuit (10) generates two clocks having phases which are equal to each other, that is, a CPU clock (CLKCPU) and a bus clock (CLKBUS). A BIU (bus interface unit) (51) controls a code bus based on the CPU clock (CLKCPU) and controls a peripheral bus based on the bus clock (CLKBUS). The clock generating circuit (10) switches a frequency of each of the CPU clock (CLKCPU) and the bus clock (CLKBUS) depending on an operation mode of an MCU. For example, a speed of the CPU clock (CLKCPU) is set to be higher than that of the bus clock (CLKBUS) in order to carry out a high-speed operation of a CPU. Also in that case, the phases of both clocks are equal to each other. Consequently, the code bus and the peripheral bus in the BIU (51) can easily be controlled.

Claims5

Dependent claims

A micro controller unit comprising:

a clock generating circuit for generating first and second clocks having equal phases to each other;
a CPU (central processing unit) to be operated based on said first clock;
a peripheral device controlled by said CPU and operated based on said second clock;
a first bus to be operated based on said first clock;
a second bus to be operated based on said second clock;
and
a BIU (bus interface unit) for controlling operation timings of said first and second buses,
wherein said clock generating circuit includes a register for holding setting of frequencies of said first and second clocks to be equal to each other or different from each other, and switches said frequencies of said first and second clocks depending on said setting held in said register with said phases of said first and second clocks maintained to be equal to each other,
said first and second clocks are input to said BIU, and
said BIU alternately switches idle periods of said first and second buses at predetermined timings which are synchronous with said first and second clocks, thereby carrying out said operation timing control.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/690,574Filed 23 Oct 2003
Priority: JP 2003-1004343 Apr 2003
Published: 21 Oct 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G06F 1/3203
Means for saving power: power management, i.e. event-based initiation of a power-saving mode
G06F 1/324
Power saving characterised by the action undertaken: by lowering clock frequency

Family

US 7,167,996 B2Related patent
US 2004/0210780 A1This patent

From the US filing history. Foreign family members aren’t listed.

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