Valid bit generation and tracking in a pipelined processor

A method comprising:

• generating a valid bit in a first pipeline stage in a pipeline including a plurality of pipeline stages;
• transmitting the valid bit to a second pipeline stage;
• setting the valid bit to an invalid value in response to receiving at least one of a stall signal and a kill signal in the second pipeline stage;
• storing the valid bit in a first latch in one of the second pipeline stage and a third pipeline stage;
• holding the valid bit in the first latch in response to receiving a stall signal;
• and
• setting the valid bit output from the first latch to an invalid value in response to receiving at least one of a stall signal and a kill signal in the third pipeline stage.

An article including instructions residing on a machine-readable medium including machine-executable instructions to cause a machine to:

• generate a valid bit in a first pipeline stage in a pipeline including a plurality of pipeline stages;
• transmit the valid bit to a second pipeline stage;
• set the valid bit to an invalid value in response to receiving at least one of a stall signal and a kill signal in the second pipeline stage;
• store the valid bit in a first latch in one of the second pipeline stage and a third pipeline stage;
• hold the valid bit in the first latch in response to receiving a stall signal;
• and
• set the valid bit output from the first latch to an invalid value in response to receiving at least one of a stall signal and a kill signal in the third pipeline stage.