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AssigneeNewisys, Inc.
InventorsCarl Zeitler, David B. Glasco, Rajesh Kota, Guru Prasadh, Richard R. Oehler, David S. Edrich
Estimating the term…
A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is associated with one of the processing nodes. Each processing node includes a processor, and a memory controller for controlling access to the associated portion of the system memory, and may contain a host bridge for facilitating communication with a plurality of I/O devices. The first point-to-point architecture is operable to facilitate first transactions between the processors and the system memory. The computer system further includes at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges. The at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.
A computer system, comprising a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory comprising a plurality of portions each of which is associated with one of the processing nodes, each processing node comprising a processor, a memory controller for controlling access to the associated portion of the system memory, and a host bridge for facilitating communication with a plurality of I/O devices, the first point-to-point architecture being operable to facilitate first transactions between the processors and the system memory, the computer system further comprising at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges, wherein the at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.
An I/O controller for use in a computer system having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory comprising a plurality of portions each of which is associated with one of the processing nodes, each processing node comprising a processor, a memory controller for controlling access to the associated portion of the system memory, and a host bridge for facilitating communication with a plurality of I/O devices, the first point-to-point architecture being operable to facilitate first transactions between the processors and the system memory, the computer system further comprising a second point-to-point architecture independent of the first point-to-point architecture for interconnecting the I/O controller and the host bridges, the I/O controller being operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.
Dependencies are inferred from the claim text.