Low-power decode circuitry for a processor
OwnerCharles F. Shelorinventor
Life of this patent
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Abstract
A processor having improved decode logic is provided. In accordance with one embodiment, the processor includes a first decoder capable of decoding a first plurality of instructions, a second decoder capable of decoding a second plurality of instructions, and special instruction logic for implementing at least one special instruction, the at least one special instruction being an instruction that the first decoder or second decoder is not designed to directly decode for execution by an execution unit in the processor. In another embodiment, a related method is provided for decoding a processor instruction.
Claims27
A processor comprising:
- fetch logic for fetching an encoded instruction;
- first decoder logic capable of decoding a plurality of encoded instructions of a first instruction set, the first decoder logic having an input to receive an encoded instruction output from the fetch logic;
- second decoder logic capable of decoding a plurality of encoded instructions of a second instruction set, the second decoding logic having an input to receive an encoded instruction output from the fetch logic;
- and
- special instruction logic associated with the second decoder logic for implementing at least one special instruction of the second instruction set, the at least one special instruction being an instruction that the second decoder logic is not designed to directly decode for execution by an execution unit in the processor.
A processor comprising:
- a plurality of decoders, each of the plurality of decoders being uniquely designed for decoding a plurality of instructions that are distinct and nonoverlapping with the instructions to be decoded by the remaining decoders;
- and
- special instruction logic associated with the at least one of the decoders for implementing at least one special instruction, the at least one special instruction being an instruction that the decoders are not designed to directly decode for execution by an execution unit in the processor.
A processor comprising:
- a first decoder capable of decoding a first plurality of instructions;
- a second decoder capable of decoding a second plurality of instructions;
- and
- special instruction logic for implementing at least one special instruction, the at least one special instruction being an instruction that the first decoder or second decoder is not designed to directly decode for execution by an execution unit in the processor.
A method for decoding a processor instruction comprising:
- determining whether the instruction is an instruction of a first instruction set or a second instruction set;
- if the instruction is determined to be an instruction of a first instruction set, then decoding the instruction using a first decoder;
- if the instruction is determined to be an instruction of a second instruction set, then directly decoding the instruction using a second decoder, if the instruction is directly, decodable by the second decoder;
- and,
- if the instruction is determined to be an instruction of the second instruction set, then causing the instruction to be executed through a call to software defined in a memory area, if the instruction is not directly decodable by the second decoder.
A method for decoding a processor instruction comprising:
- determining whether the instruction is directly decodable by a decoder within the processor;
- if the instruction is determined to be directly decodable, then decoding the instruction using the decoder;
- and
- if the instruction is determined not to be directly decodable, then causing the instruction to be executed through a call to software defined in a memory area.
A processor comprising:
- fetch logic for fetching an encoded instruction;
- decoder logic configured to decode a plurality of encoded instructions of an instruction set, the decoder logic having an input to receive an encoded instruction output from the fetch logic;
- and
- special instruction logic associated with the decoder logic for implementing at least one special instruction of the instruction set, the at least one special instruction being an instruction that the decoder logic is not designed to directly decode for execution by an execution unit in the processor.
Dependencies are inferred from the claim text.