Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device, comprising:

• forming a gate of a first transistor and a gate of a second transistor on a semiconductor substrate;
• forming a first diffusion layer having a low impurity concentration in said semiconductor substrate with the gate of said first transistor used as a mask;
• forming a second diffusion layer having a low impurity concentration in said semiconductor substrate with the gate of said second transistor used as a mask;
• forming gate side walls of the same thickness to surround the gates of said first transistor and said second transistor, respectively;
• forming a first diffusion layer having a high impurity concentration, which is positioned adjacent to said first diffusion layer having a low impurity concentration, within said semiconductor substrate, with the gate side wall of said first transistor used as a mask;
• forming a mask side wall on the gate side wall of said second transistor;
• forming a second diffusion layer having a high impurity concentration, which is positioned adjacent to said second diffusion layer having a low impurity concentration, within said semiconductor substrate, with the mask side wall used as a mask;
• and
• removing said mask side wall.

A method of manufacturing a semiconductor device, comprising:

• forming a first gate insulating film for a high voltage transistor on a semiconductor substrate;
• forming a second gate insulating film for a low voltage transistor, said second gate insulating film being thinner than said first gate insulating film;
• forming a stacked gate structure by stacking conductive materials forming the gate electrode, followed by selectively patterning by etching the stacked structure;
• introducing an impurity of a first conductivity type into the semiconductor substrate;
• depositing a first side wall material;
• forming a first side wall on the side surface of said gate electrode by selectively etching said first side wall material by means of an anisotropic etching;
• introducing an impurity into a first MOS transistor region of the semiconductor substrate in a concentration higher than that in an impurity diffusion layer of a second conductivity type;
• depositing a second side wall material and a third side wall material differing from said second side wall material;
• forming a third side wall on the side surface of said second side wall by selectively etching said third side wall material by means of an anisotropic etching;
• introducing an impurity of said first conductivity type into the second MOS transistor region of the semiconductor substrate with said third side wall used as a mask;
• depositing an interlayer insulating film on the entire surface of said semiconductor substrate;
• and
• selectively forming contact holes in said interlayer insulating film.

A method of manufacturing a semiconductor device, comprising:

• forming an element isolating region in a semiconductor substrate;
• forming a tunnel oxide film for a memory cell, a floating gate and an interlayer insulating film;
• forming a first gate insulating film for a high voltage transistor on said semiconductor substrate;
• forming a second gate insulating film for a low voltage transistor, said second gate insulating film being thinner than said first gate insulating film;
• stacking conductive materials forming a control gate and a floating gate, followed by selectively patterning successively said control gate, said interlayer insulating film, and said floating gate;
• selectively patterning the gate electrode in the peripheral circuit region;
• introducing an impurity of a second conductivity type into the semiconductor substrate in the memory cell region and the peripheral circuit region;
• depositing a first side wall material;
• forming a first side wall on the side surface of said gate electrode by selectively etching the first side wall material by an anisotropic etching;
• introducing an impurity into the first MOS transistor region of the semiconductor substrate in a concentration higher than that in said impurity diffusion layer of the second conductivity type;
• depositing a second side wall material and a third side wall material differing from said second side wall material;
• forming a third side wall on the side surface of said second side wall by selectively etching said third side wall material by an anisotropic etching;
• introducing an impurity of a first conductivity type into a second MOS transistor region of said semiconductor substrate with said third side wall used as a mask;
• removing said third side wall;
• depositing an interlayer insulating film on the entire surface of said semiconductor substrate;
• selectively forming contact holes in said interlayer insulating film;
• forming a metal wiring;
• and
• forming an insulating film on said metal wiring.

A method of manufacturing a semiconductor device, comprising:

• forming an element isolating region in a semiconductor substrate;
• forming a first gate insulating film for a high voltage transistor on said semiconductor substrate;
• forming a second gate insulating film for a low voltage transistor, said second gate insulating film being thinner than said first gate insulating film;
• stacking a conductive material layer forming a gate electrode, followed by pattering said conductive material layer by an etching;
• introducing an impurity of a second conductivity type into a first MOS transistor region of the semiconductor substrate;
• depositing a first side wall material;
• forming a first side wall on the side surface of said gate electrode by selectively etching said first side wall material by an anisotropic etching;
• introducing an impurity of a first conductivity type into a second MOS transistor region of the semiconductor substrate with said first side wall used as a mask;
• introducing an impurity into the first MOS transistor region of the semiconductor substrate in a concentration higher than that in the diffusion layer of the second conductivity type;
• depositing a second side wall material and a third side wall material differing from said second side wall material;
• forming a third side wall on the side surface of said second side wall by selectively etching said third side wall material layer by an anisotropic etching;
• introducing an impurity of the first conductivity type into a second MOS transistor region of the semiconductor substrate in a concentration higher than that in the impurity diffusion layer of the first conductivity type;
• removing the third side wall;
• depositing an interlayer insulating film on the entire substrate;
• and
• selectively forming contact holes in said interlayer insulating film.

A method of manufacturing a semiconductor device, comprising:

• introducing an impurity of a first conductivity type into a semiconductor substrate;
• forming a tunnel oxide film and a floating gate in a memory cell region;
• forming a first gate insulating film for a high voltage transistor in a peripheral circuit region;
• forming a second gate insulating film for a low voltage transistor, said second gate insulating film being thinner than said first gate insulating film;
• forming an interlayer insulating film for a memory cell;
• stacking conductive materials forming a control gate and a floating gate, followed by selectively patterning by etching said control gate, said interlayer insulating film, and said floating gate successively;
• selectively patterning the gate electrode of a peripheral circuit region;
• introducing an impurity of a second conductivity type into the memory cell region and the first MOS transistor region included in the peripheral circuit of the semiconductor substrate;
• depositing a first side wall material;
• forming a first side wall on the side surface of said gate electrode by selectively etching said first side wall material layer by an anisotropic etching;
• introducing an impurity of a first conductivity type into the second MOS transistor region of the semiconductor substrate;
• introducing an impurity into the first MOS transistor region of the semiconductor substrate in a concentration higher than that in the impurity diffusion layer of the second conductivity type;
• depositing a second side wall material and a third side wall material differing from said second side wall material;
• forming a third side wall on the side surface of the second side wall by selectively etching said third side wall material by an anisotropic etching;
• introducing an impurity into the second MOS transistor region of the semiconductor substrate in a concentration higher than that in said impurity diffusion layer of the first conductivity type;
• removing said third side wall;
• depositing an interlayer insulating film on the entire surface of the substrate;
• selectively forming contact holes in said interlayer insulating film;
• forming at least a single metal wiring;
• and
• forming an insulating film on said metal wiring.