Collar dielectric process for reducing a top width of a deep trench

A collar dielectric process, comprising the steps of:

• providing a semiconductor silicon substrate having a deep trench and a deep trench capacitor, in which the deep trench capacitor comprises a node dielectric formed on the sidewall and bottom of the deep trench and a storage node formed in the deep trench and reaching a predetermined depth;
• performing an ton implantation process to form an ion implantation area in the substrate at the top of the deep trench, wherein the ion implantation process partially surrounds a partial top of the deep trench and is adjacent to a buried strap outdiffusion region;
• removing the node dielectric until the top of the node dielectric is leveled off with the top of the storage node, thus exposing the sidewall of the deep trench outside the deep trench capacitor;
• and
• performing an oxidation process to grow a first silicon oxide layer on the exposed sidewall of the deep trench, in which the first silicon layer is outside the ion implantation area.