Semiconductor integrated circuit

A semiconductor integrated circuit having a CMOS logic gate including a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, comprising:

• a first MOS transistor region in which the first MOS transistor is formed;
• and
• a 2ath MOS transistor region in which the second MOS transistor is formed and which is placed such that a first side is in contact with a first side of said first MOS transistor region, and a 2bth MOS transistor region which is placed such that a first side is in contact with a second side opposite to the first side of said first MOS transistor region, and
• a 3ath MOS transistor region in which the first MOS transistor is formed and which is placed such that a first side is in contact with a second side opposite to the first side of said 2ath MOS transistor region, and a 3bth MOS transistor region which is placed such that one side is in contact with a second side opposite to the first side of said 2bth MOS transistor region.

A semiconductor integrated circuit having a NAND gate including first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, comprising:

• a first MOS transistor region in which the first MOS transistor is formed;
• a 3ath MOS transistor and a 3bth MOS transistor, in each of which the third MOS transistor is formed, separately arranged to be in contact with a first side of said first MOS transistor region and a second side opposite to the first side, respectively;
• a second MOS transistor region in which the second MOS transistor is formed and which is placed to be in contact with a third side perpendicular to the first side of said MOS transistor region and the second side opposite to the first side;
• and
• a 4ath MOS transistor region and a 4bth MOS transistor region, in each of which the fourth MOS transistor is formed, separately arranged to be in contact with first and second sides of said second MOS transistor region, respectively,
• wherein the first side of a source region in said first MOS transistor region is in contact with one side of a source region in said 3ath MOS transistor region,
• the second side of the source region in said first MOS transistor region is in contact with one side of a source region in said 3bth MOS transistor region,
• the first side of a drain region in said first MOS transistor region is in contact with one side of a drain region in said 3ath MOS transistor region,
• the second side of the drain region in said first MOS transistor region is in contact with one side of a drain region in said 3bth MOS transistor region,
• the first side of a source region in said second MOS transistor region is in contact with one side of a source region in said 4ath MOS transistor region,
• the second side of the source region in said second MOS transistor region is in contact with one side of a source region in said 4bth MOS transistor region,
• the first side of a drain region in said second MOS transistor region is in contact with one side of a drain region in said 4ath MOS transistor region,
• the second side of the drain region in said second MOS transistor region is in contact with one side of a drain region in said 4bth MOS transistor region,
• a first gate electrode extends above said 3ath MOS transistor region, said first MOS transistor region, and said 3bth MOS transistor region through a gate oxide film, and
• a second gate electrode extends above said 4ath MOS transistor region, said second MOS transistor region, and said 4bth MOS transistor region through the gate oxide film.

A semiconductor integrated circuit having a NAND gate including first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, and an inverter including a fifth MOS transistor of the first conductivity type and a sixth MOS transistor of the second conductivity type and having an input terminal connected to an output terminal of the NAND gate, comprising:

• a first MOS transistor region in which the first MOS transistor is formed;
• a 3ath MOS transistor and a 3bth MOS transistor, in each of which the third MOS transistor is formed, separately arranged to be in contact with a first side of said first MOS transistor region and a second side opposite to the first side, respectively;
• a second MOS transistor region in which the second MOS transistor is formed and which is placed to be in contact with a third side perpendicular to the first and second sides of said first MOS transistor region;
• a 4ath MOS transistor region and a 4bth MOS transistor region, in each of which the fourth MOS transistor is formed, separately arranged to be in contact with a first side of said second MOS transistor region and a second side opposite to the first side, respectively;
• a fifth MOS transistor region in which the fifth MOS transistor is formed and which is placed to be in contact with a fourth side perpendicular to first and second sides of said second MOS transistor region;
• and
• a sixth transistor region in which the sixth MOS transistor is formed,
• wherein the first side of a source in said first MOS transistor region is in contact with one side of a source region in said 3ath MOS transistor region,
• the second side of the source region in said first MOS transistor region is in contact with one side of a source region in said 3bth MOS transistor region,
• the first side of a drain region in said first MOS transistor region is in contact with one side of a drain region in said 3ath MOS transistor region,
• the second side of the drain region in said first MOS transistor region is in contact with one side of a drain region in said 3bth MOS transistor region,
• the first side of a source region in said second MOS transistor region is in contact with one side of a source region in said 4ath MOS transistor region;
• the second side of the source region in said second MOS transistor region is in contact with one side of a source region in said 4bth MOS transistor region,
• the first side of a drain region in said second MOS transistor region is in contact with one side of a drain region in said 4ath MOS transistor region,
• the second side of the drain region in said second MOS transistor region is in contact with one side of a drain region in said 4bth MOS transistor region,
• a third side perpendicular to the first and second sides of the source region in said second MOS transistor region is in contact with one side of a source region in said fifth MOS transistor region,
• a first gate electrode extends above said 3ath MOS transistor region, said first MOS transistor region, and said 3bth MOS transistor region through a gate oxide film,
• a second gate electrode extends above said 4ath MOS transistor region, said second MOS transistor region, and said 4bth MOS transistor region through the gate oxide film, and
• a third gate electrode is placed above said fifth MOS transistor region through the gate insulating film, a fourth gate electrode is placed above said sixth MOS transistor region through the gate insulating film, and the third gate electrode is electrically connected to the fourth gate electrode.

A semiconductor integrated circuit having a NAND gate including first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, comprising:

• a first MOS transistor region in which the first MOS transistor is formed;
• a second MOS transistor region in which the second MOS transistor is formed and which is placed such that a source region is in contact with a source region in said first MOS transistor;
• a third MOS transistor region in which the third MOS transistor is formed and which is placed such that a drain region is in contact with a drain region in said second MOS transistor;
• and
• a fourth MOS transistor region in which the fourth MOS transistor is formed and which is placed such that a drain region is in contact with a source region in said third MOS transistor,
• wherein a first gate electrode is placed above said first MOS transistor region through a gate oxide film,
• a second gate electrode is placed above said second MOS transistor region through the gate oxide film,
• a third gate electrode electrically connected to the first gate electrode is placed above said third MOS transistor region through the gate oxide film, and
• a fourth gate electrode electrically connected to the second gate electrode is placed above said fourth MOS transistor region through the gate oxide film.