Compact, low-power low-jitter digital phase-locked loop

An apparatus comprising:

• means for comparing phases of a reference signal and a feedback signal to determine a phase error between the reference and feedback signals;
• means for providing a phase-frequency detector (PFD) output comprised of PFD values, wherein each PFD value is a multi-bit value determined by the phase error and a detector gain;
• means for filtering the PFD output to obtain a loop filter (LF) output;
• means for providing an oscillator signal having a phase determined by the LF output;
• and
• means for dividing the oscillator signal in frequency by a factor of N to obtain the feedback signal, where N is one or greater.

An apparatus comprising:

• means for comparing phases of a reference signal and a feedback signal to determine a phase error between the reference and feedback signals;
• means for providing a detector output comprised of phase error values, each phase error value indicating whether the phase of the reference signal is early or late with respect to the phase of the feedback signal;
• means for filtering the detector output to obtain a loop filter (LF) output;
• and
• means for adjusting loop bandwidth of a digital phase-locked loop (PLL) based on the sequence of phase error values.

An integrated circuit comprising:

• a phase-frequency detector (PFD) operative to receive a reference signal and a feedback signal, compare phases of the reference and feedback signals, and provide a PFD output;
• a loop filter (LF) operative to receive and filter the PFD output and provide an LF output;
• and
• a current digital-to-analog converter (iDAC) operative to receive and convert the LF output to current and provide an iDAC output, the iDAC including
• a first section of L steered current sources, where L is an integer greater than one, each steered current source providing current to the iDAC output when switched on and to circuit ground when switched off, and
• a second section of P single-ended current sources, where P is an integer one or greater, each single-ended current source providing current to the iDAC output when switched on.

An integrated circuit comprising:

• a phase-frequency detector (PFD) operative to receive a reference signal and a feedback signal, compare phases of the reference and feedback signals, and provide a detector output comprised of phase error values, each phase error value indicating whether the phase of the reference signal is early or late with respect to the phase of the feedback signal;
• a scaling unit operative to receive and scale the detector output with a detector gain and provide a PFD output;
• and
• a control unit operative to receive the detector output, detect for changes in polarity of the phase error values, and adjust the detector gain based on the detected changes in phase error polarity.

An apparatus comprising:

• means for comparing phases of a reference signal and a feedback signal to determine a phase error between the reference and feedback signals;
• means for providing a detector output comprised of phase error values, each phase error value indicating whether the phase of the reference signal is early or late with respect to the phase of the feedback signal;
• means for scaling the detector output with a detector gain to obtain a phase-frequency detector (PFD) output;
• means for detecting for changes in polarity of the phase error values;
• and
• means for adjusting the detector gain based on detected changes in phase error polarity.

A method of performing phase-frequency detection (PFD), comprising:

• comparing phases of a reference signal and a feedback signal to determine a phase error between the reference and feedback signals;
• providing a detector output comprised of phase error values, each phase error value indicating whether the phase of the reference signal is early or late with respect to the phase of the feedback signal;
• scaling the detector output with a detector gain to obtain a PFD output;
• detecting for changes in polarity of the phase error values;
• and
• adjusting the detector gain based on detected changes in phase error polarity.

An integrated circuit implementing a phase-frequency detector (PFD), comprising:

• a first flip-flop operative to receive a reference signal and a reset signal and provide a first signal having transitions determined by the reference signal and being reset by the reset signal;
• a second flip-flip operative to receive a feedback signal and the reset signal and provide a second signal having transitions determined by the feedback signal and being reset by the reset signal;
• a first latch operative to receive an inverted first signal at a data input and the second signal at a clock input and provide a first output signal;
• a second latch operative to receive an inverted second signal at a data input and the first signal at a clock input and provide a second output signal;
• and
• reset circuitry operative to receive the first and second signals and provide the reset signal for the first and second flip-flops.

An apparatus comprising:

• means for receiving a detector output from a phase-frequency detector (PFD) indicating whether phase of a reference signal is early or late with respect to phase of a feedback signal;
• means for detecting for a large phase error in the detector output;
• means for detecting for a small average phase error in the detector output;
• means for increasing loop bandwidth of a phase locked loop (PLL) if the large phase error is detected;
• and
• means for decreasing the loop bandwidth if the small average phase error is detected.

A method of adjusting loop bandwidth of a digital phase-locked loop (PLL), comprising:

• receiving a detector output from a phase-frequency detector (PFD) indicating whether phase of a reference signal is early or late with respect to phase of a feedback signal;
• detecting for a large phase error in the detector output;
• detecting for a small average phase error in the detector output;
• increasing the loop bandwidth if the large phase error is detected;
• and decreasing the loop bandwidth if the small average phase error is detected.

An integrated circuit implementing a loop filter (LF) for a digital phase-locked loop (PLL), comprising:

• a first carry lookahead adder (CLA) operative to receive and sum a loop filter input and a current accumulated value and provide an updated accumulated value;
• a latch operative to receive and store the updated accumulated value from the first CLA and provide the current accumulated value;
• a first unit operative to receive and scale the current accumulated value with a first gain value and provide a first intermediate value;
• a second unit operative to receive and scale the loop filter input with a second gain value and provide a second intermediate value;
• and
• a second CLA operative to receive and sum the first and second intermediate values and provide a loop filter output.