Multi-frequency synchronizing clock signal generator

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• and
• a synchronizing clock signal generator for generating an output synchronizing clock signal, comprising:
• a synchronizing circuit having an input clock terminal coupled to receive an input clock signal having a clock frequency and further having an output clock terminal at which a synchronizing clock signal is provided, the synchronizing clock signal generated by the synchronizing circuit from the input clock signal;
• and
• a pulse generator having an input coupled to the output clock terminal, an output terminal at which the synchronizing signal is provided, and a selection terminal at which a selection signal is applied, the pulse generator generating an output synchronizing signal from the synchronizing clock signal having a pulse repetition frequency based on the selection signal.

A method for generating a synchronizing signal, comprising:

• receiving an input clock signal having a frequency;
• generating a synchronized clock signal;
• and
• generating a synchronizing pulse in response to n periods of the synchronized clock signal, the value n selected based on a selection signal.