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US 2004/0202021 A1Published application
Charge coupled eeprom device and corresponding method of operation
OwnerMassimo Atti, Christoph Demlinventors
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OwnerMassimo Atti, Christoph Demlinventors
Estimating the term…
This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate (1) having a first conductivity (p); a plurality of gate structures (CG1, FG1; . . . ; CGn, FGn) for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate (1) and electrically isolated therefrom; a plurality of wordlines (WL1-WL5), each of said gate structures (CG1, FG1; . . . ; CGn, FGn) being connected to one of said wordlines (WL1-WL5) and a group of said gate structures (CG1, FG1; . . . ; CGn, FGn) being connected to a common wordline (WL1-WL5); and a plurality of active regions (10, 20), each of said active regions (10, 20) being individually connectable to at least one of said gate structures (CG1, FG1; . . . ; CGn, FGn).
A semiconductor memory device comprising:
The semiconductor memory device according one of the preceding claims, wherein between each of said active regions (10, 20) and said at least one of said gate structures (CG1, FG1;
The semiconductor memory device according one of the preceding claims, further comprising a voltage generation means for applying individual voltages between said wordlines (WL1-WL5) and said active regions (10, 20) such that charge may be programmed, read, shifted, and erased from said gate structures (CG1, FG1;
The semiconductor memory device according one of the preceding claims, wherein doping of the substrate (1) is non-uniformly under said gate structures (CG1, FG1;
The semiconductor memory device according one of the preceding claims, further comprising a sense amplifier (SA) connected to said active regions (10, 20).
The semiconductor memory device according one of the preceding claims, further comprising a gate for separating said at least one active region (10, 20) from said gate structures (CG1, FG1;
Dependencies are inferred from the claim text.