Chip interconnection method and apparatus

A method of increasing the bandwidth of I/O integrated circuit die interconnections to an optional ancillary die on a planar, comprising:

• providing I/O connection points on a surface of a first die;
• providing corresponding 1/0 connection points on a surface of a second die;
• aligning said first and second die to obtain contact between corresponding I/O connection points;
• and
• applying an environment whereby an electrical connection is formed between corresponding connection points on said first and second die.

An integrated circuit assembly, comprising:

• a substrate;
• a first integrated circuit chip having a peripherally located set of I/O connections physically attached to corresponding circuitry on said substrate;
• and
• an inwardly disposed set of I/O connections located on an exterior surface of said integrated circuit chip for optional connection to a further integrated circuit chip.

An integrated circuit chip construction for use in a chip assembly, comprising:

• a mother chip defining a periphery, said chip including:
• first I/O circuitry at said periphery;
• and
• second I/O circuitry disposed inwardly on said chip from said periphery;
• and
• said mother chip operating in conjunction with a given ancillary chip via connections to said first I/O circuitry when both said mother chip and said ancillary chip are separately attached to a substrate;
• and
• said mother chip providing enhanced operation due to increased I/O connection bandwidth when connected to said given ancillary chip via said second I/O circuitry.

An integrated circuit chip construction for use in a chip assembly, comprising:

• a mother chip defining a periphery, said chip including:
• first I/O circuitry at said periphery;
• and
• second I/O circuitry disposed inwardly on said chip from said periphery;
• and
• said mother chip being functionally operable in the absence of a given ancillary chip and said mother chip providing enhanced operation when connected to said given ancillary chip via said second I/O circuitry.