US 2004/0201057 A1 · Method of forming a metal-insulator - metal capacitor structure in a copper damascene process sequence

Abstract

A method of forming a metal-oxide-metal (MIM), capacitor structure wherein the fabrication procedures used for the MIM capacitor structure are integrated into a process sequence used to form damascene type copper interconnect structures for CMOS type devices, has been developed. The process sequence features a copper damascene connector located overlying exposed portions of a semiconductor substrate, and underlying the MIM capacitor structure. The MIM capacitor structure, comprised a capacitor dielectric layer sandwiched between conductive capacitor plates, is protected during several selective reactive ion etching patterning procedures by an overlying anti-reflective coating (ARC), insulator shape, and by insulator spacers located on the sides of the ARC shape and on the sides of a capacitor dielectric shape. The presence of the insulator shape protects the MIM capacitor structure during a subsequent process used to define another copper danascene connector structure, overlying and contacting the MIM capacitor structure.

Claims32

Dependent claims

A method of fabricating a capacitor structure on a semiconductor substrate, comprising the steps of:

forming a first metal connector structure in an opening in a first intermetallic dielectric (IMD), layer, with said underlying metal connector structure overlying and contacting portions of said semiconductor layer;
depositing an underlying conductive layer, a capacitor dielectric layer, an overlying conductive layer, and an anti-reflective coating (ARC), layer;
performing a first patterning procedure to define a ARC shape in said ARC layer, and to define a capacitor top plate in said overlying conductive layer;
forming insulator spacers on sides of said arc shape and on sides of said capacitor top plate;
and
performing a second patterning procedure using said arc shape and said insulator spacers as an etch mask, to define a capacitor bottom plate shape in said underlying conductive layer, resulting in said capacitor structure comprised of said capacitor top plate, said capacitor dielectric shape, said capacitor bottom plate, with said capacitor structure underlying said arc shape.

3 more elements

A method of forming a metal-insulator-metal (MIM), capacitor structure, on a semiconductor substrate, comprising the steps of:

forming a first intermetallic dielectric (IMD), layer, on said semiconductor layer;
forming an opening in said first IMD layer exposing a portion of the top surface of said semiconductor substrate;
forming a first copper damascene structure in said opening in said first IMD layer;
depositing an underlying titanium nitride layer;
depositing a capacitor dielectric layer;
depositing an overlying titanium nitride layer;
depositing a silicon oxynitride, anti-reflective coating (ARC), layer;
performing a first reactive ion etching (RIE), procedure to define a silicon oxynitride ARC shape in said silicon oxynitride ARC layer, and to define a capacitor top plate in said overlying titanium nitride layer, with said first RIE procedure selective terminating at the appearance of said capacitor dielectric layer;
depositing a silicon oxide layer;
performing a second RIE procedure to form silicon oxide spacers on the sides of said silicon oxynitride ARC shape and on sides of said capacitor top plate, with said second RIE procedure also defining a capacitor dielectric shape then selectively terminating at the appearance of said underlying titanium nitride layer;
performing a third RIE procedure using said silicon oxynitride ARC shape and said silicon oxide spacers as an etch mask, to define a capacitor bottom plate shape in said underlying titanium nitride layer, with said third RIE procedure selectively terminating at the appearance of said first IMD layer, resulting in said MIM capacitor structure comprised of said capacitor top plate, said capacitor dielectric shape, said capacitor bottom plate, with said silicon oxynitride ARC shape capping said MIM capacitor structure;
depositing a second IMD layer;
performing a chemical mechanical polishing (CMP), procedure, planarizing said second IMD layer;
forming an opening in said planarized second IMD layer and in said silicon oxynitride ARC shape, exposing a portion of a top surface of said capacitor structure;
and
forming a second copper damascene structure in said opening in said planarized second IMD layer.

13 more elements

Dependencies are inferred from the claim text.

Method of forming a metal-insulator - metal capacitor structure in a copper damascene process sequence

Life of this patent

Method of forming a metal-insulator - metal capacitor structure in a copper damascene process sequence

Life of this patent

Abstract

Claims32