Method for improving etch selectivity effects in dual damascene processing

A method for forming back end of line (BEOL) interconnect structures in a semiconductor device, the method comprising:

• forming a via level dielectric on a lower metallization level;
• defining a via in said via level dielectric, thereby exposing a portion of said lower metallization level;
• depositing a sacrificial material over said via level dielectric and within said via, said sacrificial material being deposited at a thickness so as to also form a trench level dielectric;
• defining an upper metallization line trench in said trench level dielectric, said trench aligned over said via;
• and
• removing said sacrificial material from said via, thereby allowing said via and said trench to be filled with a conductive material by dual damascene processing;
• wherein the formation of said trench and the removal of said sacrificial material from said via is implemented through a single etching operation.