Method of forming a via contact structure using a dual damascene technique

A method of forming a via contact structure, the method comprising the steps of:

• forming a lower interconnection line on a semiconductor substrate;
• sequentially forming a via etch stop layer, a lower inter-metal dielectric layer, a trench etch stop layer, an upper inter-metal dielectric layer and a hard mask layer on an entire surface of the semiconductor substrate having the lower interconnection line;
• successively patterning the hard mask layer, the upper inter-metal dielectric layer, the trench etch stop layer and the lower inter-metal dielectric layer to form a preliminary via hole that exposes the via etch stop layer on the lower interconnection line;
• forming a sacrificial layer filling the preliminary via hole on the hard mask layer;
• patterning the sacrificial layer and the hard mask layer to form a first sacrificial layer pattern having an opening that crosses over the preliminary via hole and a second sacrificial layer pattern that remains in the prelimianry via hole, and to simultaneously form a hard mask pattern underneath the first sacrificial layer pattern;
• etching the upper inter-metal dielectric layer using the hard mask pattern and the trench etch stop layer as an etching mask and an etch stop layer respectivley, thereby forming a trench in the upper inter-metal dielectric layer;
• selectively removing the second sacrificial layer pattern to expose the via etch stop layer;
• and
• etching the exposed via etch stop layer to form a final via hole that exposes the lower interconnection line.