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US 2004/0175907 A1Published application
Method of fabricating a salicided device using a dummy dielectric layer between the source/drain and the gate electrode
AssigneeTaiwan Semiconductor Manfacturing Company, Ltd.
InventorsHorng-Huei Tseng, Da-Chi Lin, Kuo-Nan Yang, Chenming Hu
Life of this patent
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Abstract
A new method is provided for the creation of CMOS devices. A sacrificial layer is deposited over a silicon substrate. This sacrificial layer is instrumental in creating gate spacers and in doing so serves to separate the gate from the source/drain regions in a self-aligned manner.
Claims65
A method for the creation of a self-aligned gate electrode, comprising:
- providing a substrate, an first active surface region having been defined in the substrate, a second surface area having been defined within the first active surface area for creation of a gate electrode aligned therewith;
- creating a patterned and etched sacrificial layer over the substrate and surrounding the second surface area;
- etching a shallow trench into the substrate bounded by the patterned and etched sacrificial layer;
- and
- completing creation of a gate electrode self-aligned with the shallow trench by providing gate spacers, gate dielectric, gate material and gate impurity implantations, including salicidation of contact surfaces to the gate electrode.
2 more elements
A method for the creation of a self-aligned gate electrode, comprising:
- providing a substrate, a first surface area having been defined over the substrate for the creation of a gate electrode aligned therewith;
- creating regions of field isolation oxide in the substrate, the regions of field oxide bounding the first surface area of the substrate;
- depositing a sacrificial layer over the substrate;
- patterning and etching the sacrificial layer, creating an opening through the sacrificial layer aligned with the first surface are of the substrate, penetrating the substrate to form a shallow trench therein in alignment with the opening through the sacrificial layer;
- depositing a conformal layer of dielectric over the patterned and etched sacrificial layer, including inside surfaces of the trench created in the substrate;
- applying an etchback to the deposited layer of dielectric, forming spacers over sidewalls of the shallow trench created in the substrate, exposing the patterned and etched sacrificial layer, exposing a bottom surface of the shallow trench created in the substrate;
- forming a layer of gate dielectric over the exposed bottom surface of the shallow trench;
- depositing a layer of gate electrode material over the patterned and etched sacrificial layer, including exposed surfaces of the spacers created over sidewalls of the shallow trench;
- removing the deposited gate electrode material from the patterned and etched sacrificial layer, exposing the patterned and etched sacrificial layer, creating a layer of gate electrode material bounded by the gate spacers;
- removing the sacrificial layer from the substrate;
- performing source/drain impurity implantations self-aligned with the created layer of gate electrode material bounded by the gate spacers;
- depositing a thin layer of metal;
- and
- applying heat-treatment to the deposited thin layer of metal, saliciding the thin layer of metal.
11 more elements
A method for the creation of a self-aligned gate electrode, comprising:
- providing a substrate, an first active surface region having been defined in the substrate, a second surface area having been defined within the first active surface area for creation of a gate electrode aligned therewith;
- creating a patterned and etched sacrificial layer over the substrate and surrounding the second surface area;
- etching a shallow trench into the substrate bounded by the patterned and etched sacrificial layer;
- and
- completing creation of a gate electrode self-aligned with the shallow trench by providing gate spacers, gate dielectric, gate material and gate impurity implantations.
2 more elements
A method for the creation of a self-aligned gate electrode, comprising:
- providing a substrate, a first surface area having been defined over the substrate for the creation of a gate electrode aligned therewith;
- creating regions of field isolation oxide the substrate, the regions of field oxide bounding the first surface area of the substrate;
- depositing a sacrificial layer over the substrate;
- patterning and etching the sacrificial layer, creating an opening through the sacrificial layer aligned with the first surface are of the substrate, penetrating the substrate to form a shallow trench therein in alignment with the opening through the sacrificial layer;
- depositing a conformal layer of dielectric over the patterned and etched sacrificial layer, including inside surfaces of the trench created in the substrate;
- applying an etchback to the deposited layer of dielectric, forming spacers over sidewalls of the shallow trench created in the substrate, exposing the patterned and etched sacrificial layer, exposing a bottom surface of the shallow trench created in the substrate;
- forming a layer of gate dielectric over the exposed bottom surface of the shallow trench;
- depositing a layer of gate electrode material over the patterned and etched sacrificial layer, including exposed surfaces of the spacers created over sidewalls of the shallow trench;
- removing the deposited gate electrode material from the patterned and etched sacrificial layer, exposing the patterned and etched sacrificial layer, creating a layer of gate electrode material bounded by the gate spacers;
- removing the sacrificial layer from the substrate;
- and
- performing source/drain impurity implantations self-aligned with the created layer of gate electrode material bounded by the gate spacers.
9 more elements
A method for the creation of a self-aligned gate electrode, comprising:
- providing a substrate, a first surface area having been defined over the substrate for the creation of a gate electrode aligned therewith;
- creating regions of field isolation oxide in the substrate, the regions of field oxide bounding the first surface area of the substrate;
- depositing a sacrificial layer over the substrate;
- patterning and etching the sacrificial layer, creating an opening through the sacrificial layer aligned with the first surface are of the substrate, penetrating the substrate to form a shallow trench therein in alignment with the opening through the sacrificial layer;
- depositing a conformal layer of dielectric over the patterned and etched sacrificial layer, including inside surfaces of the trench created in the substrate;
- applying an etchback to the deposited layer of dielectric, forming spacers over sidewalls of the shallow trench created in the substrate, exposing the patterned and etched sacrificial layer, exposing a bottom surface of the shallow trench created in the substrate;
- forming a layer of gate dielectric over the exposed bottom surface of the shallow trench;
- depositing a layer of gate electrode material over the patterned and etched sacrificial layer, including exposed surfaces of the spacers created over sidewalls of the shallow trench;
- removing the deposited gate electrode material from the patterned and etched sacrificial layer using methods of Chemical Mechanical Polishing (CMP), exposing the patterned and etched sacrificial layer, creating a layer of gate electrode material bounded by the gate spacers;
- removing the sacrificial layer from the substrate;
- performing source/drain impurity implantations self-aligned with the created layer of gate electrode material bounded by the gate spacers;
- depositing a thin layer of metal;
- and
- applying heat-treatment to the deposited thin layer of metal, saliciding the thin layer of metal.
11 more elements
A method for the creation of a self-aligned gate electrode, comprising:
- providing a substrate, a first surface area having been defined over the substrate for the creation of a gate electrode aligned therewith;
- creating regions of field isolation oxide in the substrate, the regions of field oxide bounding the first surface area of the substrate;
- depositing a sacrificial layer over the substrate;
- patterning and etching the sacrificial layer, creating an opening through the sacrificial layer aligned with the first surface are of the substrate, penetrating the substrate to form a shallow trench therein in alignment with the opening through the sacrificial layer;
- depositing a conformal layer of dielectric over the patterned and etched sacrificial layer, including inside surfaces of the trench created in the substrate;
- applying an etchback to the deposited layer of dielectric, forming spacers over sidewalls of the shallow trench created in the substrate, exposing the patterned and etched sacrificial layer, exposing a bottom surface of the shallow trench created in the substrate;
- forming a layer of gate dielectric over the exposed bottom surface of the shallow trench;
- depositing a layer of gate electrode material over the patterned and etched sacrificial layer, including exposed surfaces of the spacers created over sidewalls of the shallow trench;
- removing the deposited gate electrode material from the patterned and etched sacrificial layer by methods of Chemical Mechanical Polishing (CMP), exposing the patterned and etched sacrificial layer, creating a layer of gate electrode material bounded by the gate spacers;
- removing the sacrificial layer from the substrate;
- and
- performing source/drain impurity implantations self-aligned with the created layer of gate electrode material bounded by the gate spacers.
9 more elements
Dependencies are inferred from the claim text.