EEPROM with reduced manufacturing complexity

A method of manufacturing a semiconductor device, comprising:

• implanting source and drain regions having similar doping profiles in a semiconductor substrate, thereby defining a channel region extending from said source region to said drain region;
• locating a dielectric layer over said source and drain regions, said dielectric layer having first and second thicknesses wherein said second thickness is substantially less than said first thickness and is partially located over said channel region;
• and
• forming a gate over said dielectric layer wherein said second thickness is located between an end of said gate and one of said source and drain regions.

An integrated circuit, comprising:

• transistors formed over or in a semiconductor substrate;
• memory cells, including:
• source and drain regions located in said semiconductor substrate and having similar doping profiles;
• a channel region extending from said source region to said drain region;
• a dielectric layer located over said source and drain regions and having first and second thicknesses wherein said second thickness is substantially less than said first thickness and is partially located over said channel region;
• and
• a gate located over said dielectric layer wherein said second thickness is located between an end of said gate and one of said source and drain regions;
• and
• interconnects connecting said transistors and said memory cells to form an integrated circuit.