Magnetoresistive random access memory, and manufacturing method thereof
AssigneeHynix Semiconductor Inc.
InventorSeon Yong Cha
Life of this patent
Estimating the term…
Abstract
The present invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof. The whole cells are connected to each other by using a substrate as a ground terminal and a vertical structure field effect transistor (FET) for connecting the cells to the bit line. Thus, the MRAM is easily manufactured without requiring a special process for isolation of each cell. The MRAM uses the vertical structure FET to simplify the whole manufacturing process. An MTJ cell mask process which is essential in a general horizontal structure FET is omitted, to improve a speed of the MRAM and attain high integration of the MRAM.
Claims13
A magnetoresistive random access memory comprising a vertical structure field effect transistor,
- wherein the vertical structure field effect transistor has its channel column and drain area sequentially formed on an insulation substrate, its source area formed on the insulation substrate on which the channel column has not been formed, and its read word lines formed around the channel column to serve as a gate,
- a contact line, a magnetic tunnel junction cell, a bit line and a write word line are sequentially formed on the drain area, and
- patterns of the magnetic tunnel junction cell are formed according to a self-alignment method, without requiring a special mask process for forming the patterns.
A manufacturing method of a magnetoresistive random access memory, comprising:
- a first process for forming a vertical structure field effect transistor by sequentially forming a channel columns and a drain area on an insulation substrate, a source area on the insulation substrate on which the channel columns have not been formed, and read word lines around the channel columns serving as gates;
- a second process for forming a magnetic tunnel junction cell and a bit line on the vertical structure field effect transistor, and patterning the magnetic tunnel junction cell according to a self-alignment method aligning the magnetic tunnel junction cell in a matrix shape, by using the bit line and read word line masks;
- and
- a third process for patterning and etching a write word line on the bit line in the right angle direction to the bit line.
Dependencies are inferred from the claim text.