Method and apparatus for handling split response transactions within a peripheral interface of an I/O node of a computer system
AssigneeAdvanced Micro Devices, Inc.
InventorTahsin Askar
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorTahsin Askar
Estimating the term…
A method and apparatus for handling split response transactions within a peripheral interface of an I/O node of a computer system. An apparatus includes a first buffer circuit coupled to receive packet commands from a requesting node. The first buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected packet commands that belong to the respective virtual channel. The apparatus also includes a bus interface circuit which may be configured to cause a bus cycle corresponding to a given packet command stored within the first buffer circuit to be initiated upon a peripheral bus. Further, the apparatus includes a second buffer circuit coupled to store the given packet command in response to receiving a split response from a target of the bus cycle.
A method for handling incomplete responses in a peripheral interface of an input/output node of a computer system, said method comprising:
An apparatus for handling incomplete responses in a peripheral interface of an input/output node of a computer system, said apparatus comprising:
Dependencies are inferred from the claim text.