US 2004/0170045 A1 · Ferroelectric-type nonvolatile semiconductor memory · patentgrep

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Abstract

A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential is provided to the bit line connected to the one of said memory cells, and a reference potential of the same level is provided to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are provided to the bit lines connected to the memory cells belonging to the different thermal history groups.

Claims21

Dependent claims

A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells,

each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer,
a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes,
data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines,
a pair of the bit lines being connected to a differential sense amplifier,
wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells,
when another data stored in the other of said memory cells is read out, a reference potential is provided to the bit line connected to the one of said memory cells, and
a reference potential of the same level is provided to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are provided to the bit lines connected to the memory cells belonging to the different thermal history groups.

4 more elements

A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit;

said first memory unit having;
(A-1) a first bit line,
(B-1) a first transistor for selection,
(C-1) first sub-memory units which are N in number (N≧2) and each of which is composed of memory cells which are M in number (M≧2), and
(D-1) plate lines which are M×N in number, and
said second memory unit having;
(A-2) a second bit line,.
(B-2) a second transistor for selection,
(C-2) second sub-memory units which are N in number and each of which is composed of memory cells which are M in number, and
(D-2) the plate lines which are M×N in number and are shared with the plate limes which are M×N in number and constitute said first memory unit,
wherein the first sub-memory unit of an n-th layer (n=1, 2 . . . , N) and the second sub-memory unit of the n-th layer are formed on the same insulating layer,
the first sub-memory unit of an n′-th layer (n′=2 . . . N) and the second sub-memory unit of the n′-th layer are stacked on the first sub-memory unit of the (n′−1)-th layer and the second sub-memory unit of the (n′−1)-th layer through the insulating layer,
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the first memory unit, the first electrodes of the memory cells constituting the first sub-memory unit of the n-th layer are in common with the first sub-memory unit of the n-th layer, said common first electrode is connected to the first bit line through the first transistor for selection, and the second electrode of the memory cell in an m-th-place (m=1, 2 . . . M) is connected to the common plate line in the [(n−1)M+m]-th-place,
in the second memory unit, the first electrodes of the memory cells constituting the second sub-memory unit of the n-th layer are in common with the second sub-memory unit of the n-th layer, said common first electrode is connected to the second bit line through the second transistor for selection, and the second electrode of the memory cell in the m-th-place is connected to the common plate line in the [(n−1)M+m]-th-place,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the same thermal history with regard to their production processes,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the thermal history different from the thermal history of the memory cells constituting the first sub-memory unit of a k-th layer (k≠n) and the memory cells constituting the second sub-memory unit of the k-th layer,
the memory cell in the m-th-place constituting the first sub-memory unit of the n-th layer in the first memory unit and the memory cell in the m-th-place constituting the second sub-memory unit of the n-th layer in the second memory unit form a pair to store data of 1 bit each,
a reference potential having an n-th potential is provided to the second bit line when data stored in the memory cell constituting the first sub-memory unit of the n-th layer in the first memory unit is read out,
a reference potential having an n-th potential is provided to the first bit line when data stored in the memory cell constituting the second sub-memory unit of the n-th layer in the second memory unit is read out, and
the n-th potential differs from the k-th potential (k≠n).

18 more elements

A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit;

said first memory unit having;
(A-1) a first bit line,
(B-1) first transistors for selection which are N in number (N≧2),
(C-1) first sub-memory units which are N in number and each of which is composed of memory cells which are M in number (M≧2), and
(D-1) plate lines which are M in number and each of which is shared with each memory cell constituting each of the first sub-memory units which are N in number, between or among the first sub-memory units which are N in number, and
said second memory unit having;
(A-2) a second bit line,
(B-2) second transistors for selection which are N in number,
(C-2) second sub-memory units which are N in number and each of which is composed of memory cells which are M in number, and
(D-2) the plate lines which are M in number, each of which is shared with each memory cell constituting each of the second sub-memory units which are N in number, between or among the second sub-memory units which are N in number, and which are shared with the plate lines which constitute said first memory unit and are M in number,
wherein the first sub-memory unit of an n-th layer (n=1, 2 . . . N) and the second sub-memory unit of the n-th layer are formed on the same insulating layer,
the first sub-memory unit of an n′-th layer (n′=2 . . . N) and the second sub-memory unit of the n′-th layer are stacked on the first sub-memory unit of the (n′−1)-th layer and the second sub-memory unit of the (n′−1)-th layer through the insulating layer,
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the first memory unit, the first electrodes of the memory cells constituting the first sub-memory unit of the n-th layer are in common with the first sub-memory unit of the n-th layer, said common first electrode is connected to the first bit line through the n-th-place first transistor for selection, and the second electrode of the memory cell in an m-th-place (m=1, 2 . . . M) is connected to the common plate line in the m-th-place,
in the second memory unit, the first electrodes of the memory cells constituting the second sub-memory unit of the n-th layer are in common with the second sub-memory unit of the n-th layer, said common first electrode is connected to the second bit line through the n-th-place second transistor for selection, and the second electrode of the memory cell in the m-th-place is connected to the common plate line in the m-th-place,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the same thermal history with regard to their production processes,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the thermal history different from the thermal history of the memory cells constituting the first sub-memory unit of a k-th layer (k≠n) and the memory cells constituting the second sub-memory unit of the k-th layer,
the memory cell in the m-th-place constituting the first sub-memory unit of the n-th layer in the first memory unit and the memory cell in the m-th-place constituting the second sub-memory unit of the n-th layer in the second memory unit form a pair to store data of 1 bit each,
a reference potential having an n-th potential is provided to the second bit line when data stored in the memory cell constituting the first sub-memory unit of the n-th layer in the first memory unit is read out,
a reference potential having an n-th potential is provided to the first bit line when data stored in the memory cell constituting the second sub-memory unit of the n-th layer in the second memory unit is read out, and
the n-th potential differs from the k-th potential (k≠n).

18 more elements

A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit;

said first memory unit having;
(A-1) a first bit line,
(B-1) first transistors for selection which are N in number (N≧2),
(C-1) first sub-memory units which are N in number and each of which is composed of memory cells which are M in number (M≧2),
(D-1) plate lines which are M in number and each of which is shared with each memory cell constituting each of the first sub-memory units which are N in number, between or among the first sub-memory units which are N in number,
(E-1) a first transistor for writing-in,
(F-1) a first transistor for detection, and
(G-1) a first transistor for read-out, and
said second memory unit having;
(A-2) a second bit line,
(B-2) second transistors for selection which are N in number,
(C-2) second sub-memory units which are N in number and each of which is composed of memory cells which are M in number,
(D-2) the plate lines which are M in number, each of which is shared with each memory cell constituting each of the second sub-memory units which are N in number, between or among the second sub-memory units which are N in number, and which are shared with the plate lines which constitute said first memory unit and are M in number,
(E-2) a second transistor for writing-in,
(F-2) a second transistor for detection, and
(G-2) a second transistor for read-out,
wherein the first sub-memory unit of an n-th layer (n=1, 2 . . . N) and the second sub-memory unit of the n-th layer are formed on the same insulating layer,
the first sub-memory unit of an n′-th layer (n′=2 . . . N) and the second sub-memory unit of the n′-th layer are stacked on the first sub-memory unit of the (n′−1)-th layer and the second sub-memory unit of the (n′−1)-th layer through the insulating layer,
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the first memory unit, the first electrodes of the memory cells constituting the first sub-memory unit of the n-th layer are in common with the first sub-memory unit of the n-th layer, said common first electrode is connected to the first bit line through the n-th-place first transistor for selection and the first transistor for writing-in, and the second electrode of the memory cell in an m-th-place (m=1, 2 . . . M) is connected to the common plate line in the m-th-place,
in the second memory unit, the first electrodes of the memory cells constituting the second sub-memory unit of the n-th layer are in common with the second sub-memory unit of the n-th layer, said common first electrode is connected to the second bit line through the n-th-place second transistor for selection and the second transistor for writing-in, and the second electrode of the memory cell in the m-th-place is connected to the common plate line in the m-th-place,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th, layer have the thermal history with regard to their production processes,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the thermal history different from the thermal history of the memory cells constituting the first sub-memory unit of a k-th layer (k≠n) and the memory cells constituting the second sub-memory unit of the k-th layer,
the memory cell in the m-th-place constituting the first sub-memory unit of the n-th layer in the first memory unit and the memory cell in the m-th-place constituting the second sub-memory unit of the n-th layer in the second memory unit form a pair to store data of 1 bit each,
one end of the first transistor for detection is connected to a first wiring having a predetermined potential, and the other end thereof is connected to the first bit line through the first transistor for read-out,
one end of the second transistor for detection is connected to a second wiring having a predetermined potential, and the other end thereof is connected to the second bit line through the second transistor for read-out,
the n-th-place first transistor for selection and the first transistor for read-out are brought into a conducting state when data stored in the memory cell constituting the first sub-memory unit of the n-th layer in the first memory unit is read out, the operation of the first transistor for detection is controlled with a potential that occurs in the common first electrode on the basis of data stored in said memory cell, and a reference potential having an n-th potential is provided to the second bit line,
the n-th-place second transistor for selection and the second transistor for read-out are brought into a conducting state when data stored in the memory cell constituting the second sub-memory unit of the n-th layer in the second memory unit is read out, the operation of the second transistor for detection is controlled with a potential that occurs in the common first electrode on the basis of data stored in said memory cell, and a reference potential having an n-th potential is provided to the first bit line, and
the n-th potential differs from the k-th potential (k≠n).

26 more elements

A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit;

said first memory unit having;
(A-1) a first bit line,
(B-1) a first transistor for selection,
(C-1) first sub-memory units which are N in number (N≧2) and each of which is composed of memory cells which are M in number (M≧2), and
(D-1) plate lines which are M×N in number, and
said second memory unit having;
(A-2) a second bit line,
(B-2) a second transistor for selection,
(C-2) second sub-memory units which are N in number and each of which is composed of memory cells which are M in number, and
(D-2) the plate lines which are M×N in number and are shared with the plate lines which are M×N in number and constitute said first memory unit,
wherein the first sub-memory unit of an n-th layer (n=1, 2 . . . N) and the second sub-memory unit of the n-th layer are formed on the same insulating layer,
the first sub-memory unit of an n′-th layer (n′=2 . . . N) and the second sub-memory unit of the n′-th layer are stacked on the first sub-memory unit of the (n′−1)-th layer and the second sub-memory unit of the (n′−1)-th layer through the insulating layer,
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the first memory unit, the first electrodes of the memory cells constituting first sub-memory unit of the n-th layer are in common with the first sub-memory unit of the n-th layer, said common first electrode is connected to the first bit line through the first transistor for selection, and the second electrode of the memory cell in an m-th-place (m=1, 2 . . . M) is connected to the common plate line in the [(n−1)M+m]-th-place,
in the second memory unit, the first electrodes of the memory cells constituting the second sub-memory unit of the n-th layer are in common with the second sub-memory unit of the n-th layer, said common first electrode is connected to the second bit line through the second transistor for selection, and the second electrode of the memory cell in the m-th-place is connected to the common plate line in the [(n−1)M+m]-th-place,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the same thermal history with regard to their production processes,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the thermal history different from the thermal history of the memory cells constituting the first sub-memory unit of a k-th layer (k≠n) and the memory cells constituting the second sub-memory unit of the k-th layer, and
the memory cell in the m-th-place constituting the first sub-memory unit of the n-th layer in the first memory unit and the memory cell in the m-th-place constituting the second sub-memory unit of the n-th layer in the second memory unit form a pair to store complement data.

15 more elements

A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit;

said first memory unit having;
(A-1) a first bit line,
(B-1) first transistors for selection which are N in number (N≧2),
(C-1) first sub-memory units which are N in number and each of which is composed of memory cells which are M in number (M≧2), and
(D-1) plate lines which are M in number and each of which is shared with each memory cell constituting each of the first sub-memory units which are N in number, between or among the first sub-memory units which are N in number, and
said second memory unit having;
(A-2) a second bit line,
(B-2) second transistors for selection which are N in number,
(C-2) second sub-memory units which are N in number and each of which is composed of memory cells which are M in number, and
(D-2) the plate lines which are M in number, each of which is shared with each memory cell constituting each of the second sub-memory unit which are N in number, between or among the second sub-memory units which are N in number, and which are shared with the plate lines which are M in number and constitute said first memory unit,
wherein the first sub-memory unit of an n-th layer (n=1, 2 . . . N) and the second sub-memory unit of the n-th layer are formed on the same insulating layer,
the first sub-memory unit of an n′-th layer (n′=2 . . . N) and the second sub-memory unit of the n′-th layer are stacked on the first sub-memory unit of the (n′−1)-th layer and the second sub-memory unit of the (n′−1)-th layer through the insulating layer, and
each memory cell comprises a first electrode, a ferroelectric layer and a second electrode,
in the first memory unit, the first electrodes of the memory cells constituting the first sub-memory unit of the n-th layer are in common with the first sub-memory unit of the n-th layer, said common first electrode is connected to the first bit line through the n-th-place first transistor for selection, and the second electrode of the memory cell in an m-th-place (m=1, 2 . . . M) is connected to the common plate line in the m-th-place,
in the second memory unit, the first electrodes of the memory cells constituting the second sub-memory unit of the n-th layer are in common with the second sub-memory unit of the n-th layer, said common first electrode is connected to the second bit line through the n-th-place second transistor for selection, and the second electrode of the memory cell in the m-th-place is connected to the common plate line in the m-th-place,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the same thermal history with regard to their production processes,
the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the thermal history different from the thermal history of the memory cells constituting the first sub-memory unit of a k-th layer (k≠n) and the memory cells constituting the second sub-memory unit of the k-th layer, and
the memory cell in the m-th-place constituting the first sub-memory unit of the n-th layer in the first memory unit and the memory cell in the m-th-place constituting the second sub-memory unit of the n-th layer in the second memory unit form a pair to store complement data.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/793,349Filed 3 Mar 2004
Priority: JP JP2001-24725516 Aug 2001
Published: 2 Sep 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10B 53/00
Ferroelectric ram [feram] devices comprising ferroelectric memory capacitors
G11C 11/22
Using electric elements: using ferroelectric elements
H10B
Electronic memory devices
G11C
Static stores

Family

Application10/217,374Division · filed 13 Aug 2002
Application10/793,349Division · filed 3 Mar 2004
US 2003/0058683 A1Published application
US 6,888,735 B2Related patent
US 6,934,175 B2Related patent
US 2004/0170045 A1This patent

From the US filing history. Foreign family members aren’t listed.

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