Etch back of interconnect dielectrics

A method of manufacturing a semiconductor wafer comprising:

• forming a front-end structure over a semiconductor substrate;
• forming a first layer of low-k material over said front-end structure,
• forming holes through said first layer of low-k material;
• forming a metal layer over said first layer of low-k material, said metal layer also filling said holes;
• reducing a height of said metal layer to form first layer metal interconnects and expose a top surface of said first layer of low-k material;
• and
• etching a top surface of said semiconductor wafer to make a height of said first layer of low-k material less than a height of said first layer metal interconnects.

An integrated circuit comprising:

• a semiconductor substrate;
• a front-end structure coupled to said semiconductor substrate;
• and
• a first layer of a back-end structure coupled to said front-end structure, said first layer of a back end structure having first layer interconnects and first layer dielectrics;
• wherein a height of said first layer dielectrics is less than a height of said first layer interconnects.

An integrated circuit comprising:

• a semiconductor substrate;
• a front-end structure coupled to said semiconductor substrate;
• a first layer of a back-end structure coupled to said front-end structure, said first layer of a back end structure having first layer interconnects and first layer dielectrics, wherein a height of said first layer dielectrics is less than a height of said first layer interconnects;
• a barrier layer coupled to said first layer of a back-end structure;
• and
• a second layer of a back-end structure coupled to said barrier layer, said second layer of a back-end structure having second layer interconnects and second layer dielectrics, wherein a height of said second layer dielectrics is less than a height of said second layer interconnects;
• further wherein at least one of said first layer interconnects is electrically connected to at least one of said second layer interconnects at an interface region.

An integrated circuit comprising:

• a semiconductor substrate;
• a front-end structure coupled to said semiconductor substrate;
• a first layer of a back-end structure coupled to said front-end structure, said first layer of a back end structure having first layer interconnects and first layer dielectrics, wherein a height of said first layer dielectrics is less than a height of said first layer interconnects;
• and
• a second layer of a back-end structure coupled to said first layer of a back-end structure, said second layer of a back-end structure having second layer interconnects and second layer dielectrics, wherein a height of said second layer dielectrics is less than a height of said second layer interconnects;
• further wherein at least one of said first layer interconnects is electrically connected to at least one of said second layer interconnects at an interface region.