Nonvolatile semiconductor memory device with improved gate oxide film arrangement

A nonvolatile semiconductor memory device comprising:

• a memory cell region composed of a memory cell array comprising a plurality of memory cells arranged as a matrix, each of said memory cells comprising first MOS field effect transistors each having a first well region formed in a semiconductor substrate, a first diffusion layer formed in said first well region and designed to function as source and drain, a floating gate formed on said well with the interposition of a tunnel dielectric film, and a control gate formed above said well with the interposition of an interpoly dielectric film, and
• a peripheral circuit region provided with second MOS field effect transistors each having a second well region formed in the semiconductor substrate, a second diffusion layer formed in said second well region and designed to function as source and drain, and first gate electrodes formed on said second well with the interposition of a first gate insulating film, and third MOS field effect transistors each having a third well region formed in the semiconductor substrate, a third diffusion layer formed in said third well region and designed to function as source and drain, and second gate electrodes formed on said third well with the interposition of a second insulating film which is greater than said first gate insulating film in thickness,
• wherein isolation in said peripheral circuit region is effected by shallow groove isolation method, and said second gate insulating film comprises a first insulating film deposited on the semiconductor substrate.

A nonvolatile semiconductor memory device comprising:

• a memory cell region composed of a memory cell-array comprising a plurality of memory cells arranged as a matrix, each memory cell comprising first MOS field effect transistors each having a first well region formed in a semiconductor substrate, a first diffusion layer formed in said first well region and designed to function as source and drain, a floating gate formed on said well with the interposition of a tunnel dielectric film, and a control gate formed above said floating gate with the interposition of an interpoly dielectric film, and
• a peripheral circuit region provided with second MOS field effect transistors each having a second well region formed in the semiconductor substrate, a second diffusion layer formed in said second well region and designed to function as source and drain, and first gate electrodes formed on said second well with the interposition of a first insulating film, and third MOS field effect transistors each having a third well region formed in the semiconductor substrate, a third diffusion layer formed in said third well region and designed to function as source and drain, and second gate electrodes formed on said third well with the interposition of a second insulating film which is greater than said first gate insulating film in thickness,
• wherein isolation in said peripheral circuit region is effected by shallow groove isolation method, and the second insulating film comprises a first insulating film formed by thermally oxidizing the semiconductor substrate and a second insulating film deposited on said first insulating film.

A process for producing a nonvolatile semiconductor memory device comprising a plurality of memory cells each having a floating gate formed on a semiconductor substrate with the interposition of a tunnel dielectric film and a control gate formed on said floating gate with the interposition of an interpoly dielectric film, and a plurality of field effect transistors each having gate electrodes formed on the semiconductor substrate with the interposition of a gate insulating film, said process comprising the steps of:

• forming a shallow groove isolation region on a semiconductor substrate;
• forming a tunnel dielectric film on the semiconductor substrate surface in said memory cell formed region by thermal oxidation method,
• depositing a first polycrystalline Si film which becomes said floating gate, and then removing the first polycrystalline Si film in said field effect transistor formed region;
• depositing a first silicon oxide film which becomes the first portion of said gate insulating film, and then removing the first silicon oxide film in said memory cell formed region;
• depositing a second silicon oxide film which becomes said interpoly dielectric film and a second portion of said gate insulating film;
• and
• depositing a second polycrystalline Si film which becomes said control gate and said gate electrodes.

A process for producing a nonvolatile semiconductor memory device comprising a plurality of memory cells each having a floating gate formed on a semiconductor substrate with the interposition of a tunnel dielectric film and a control gate formed on said floating gate with the interposition of an interpoly dielectric film, and a plurality of field effect transistors each having gate electrodes formed on the semiconductor substrate with the interposition of a gate insulating film, said process comprising the steps of:

• forming a shallow groove isolation region on the semiconductor substrate;
• forming a tunnel dielectric film on the semiconductor substrate surface in the memory cell formed region by thermal oxidation method;
• depositing a first polycrystalline Si film which becomes said floating gate, and then removing the first polycrystalline Si film in said field effect transistor formed region;
• forming a first silicon oxide film, which becomes a first portion of said gate insulating film, on the semiconductor substrate surface in the field effect transistor formed region by thermal oxidation method;
• depositing a second silicon oxide film which becomes said interpoly dielectric film and a second portion of said gate insulating film;
• and
• depositing a second polycrystalline Si film which becomes said control gate and said gate electrodes.

A process for producing a nonvolatile semiconductor memory device comprising a plurality of memory cells each having a floating gate formed on a semiconductor substrate with the interposition of a tunnel dielectric film and a control gate formed on said floating gate with the interposition of an interpoly dielectric film, and a plurality of field effect transistors each having gate electrodes formed on the semiconductor substrate with the interposition of a gate insulating film, said process comprising the steps of:

• forming a shallow groove isolation region on a semiconductor substrate;
• depositing a first silicon oxide film which becomes a first portion of said gate insulating film, and then removing said first silicon oxide film in the memory cell formed region;
• forming a tunnel dielectric film on the semiconductor substrate surface in the memory cell formed region and forming a second silicon oxide film which becomes a second portion of said gate insulating film between said semiconductor substrate in the transistor formed region and said first silicon oxide film, both by thermal oxidation method;
• depositing a first polycrystalline Si film which becomes said floating gate and said gate electrodes;
• depositing a third silicon oxide film which becomes said interpoly dielectric film;
• and
• depositing a second polycrystalline Si film which becomes said control gate.