Structure and fabricating method to make a cell with multi-self-alignment in split gate flash

A new method of fabricating a split gate flash memory device with multi-self-alignment, comprising:

• forming active regions, arranged in rows, disposed over a semiconductor region and separated by isolation regions;
• forming structural elements that are arranged in identical order along the rows of active regions, there being at this point three structural elements in the arrangements:
• unfinished floating gate, sacrificial and empty elements denoted by F*, Y and X respectively, which are arranged as . . . YXF*XF*XYXF*XF*XY . . . so that empty elements fall between unfinished floating gate elements on both sides and between unfinished floating gate and sacrificial elements, sacrificial elements being the same in structure as unfinished floating gate elements except that they are to he removed, and where unfinished floating gate elements and sacrificial elements are created by forming a gate insulator layer over said semiconductor region and patterning said gate insulator layer to exist only in unfinished floating gate and sacrificial element areas, forming floating gates conductive layers that are disposed over said gate insulator layer, and forming a floating gate insulator layer by depositing and patterning an insulator layer into parallel strips perpendicular to the row direction, so that the strips are disposed over corresponding unfinished floating gate elements and sacrificial elements;
• forming first a blanket conformal insulator layer and then a second conformal insulator layer within those empty elements that are between unfinished floating gate elements and extending over a portion of the adjacent unfinished floating gate elements, and performing spacer etching procedures on that portion of the blanket conformal insulator layer that is within those empty elements that are between unfinished floating gate elements and extending over a portion of the adjacent unfinished floating gate elements and on the second conformal insulator layer to form insulating spacers, which finishes the floating gate elements;
• performing a source ion implantation through the empty elements that are between floating gate elements and annealing to form source regions that are self aligned to adjacent floating gate elements and extend within said semiconductor region to under the adjoining floating gate regions;
• forming conductive source pick up lines, in those empty element that are between floating gate elements so that they are self aligned to the adjacent floating gate elements and to the source regions, and conductive word lines, in those empty elements that arc between floating gate elements and sacrificial elements so that they are self aligned to the adjacent floating gate elements and adjacent sacrificial elements, by depositing a conductive layer and etching back so that the remaining conductive layer is well within what were the empty elements, and then forming a source element and word line element insulator layer to substantially fill what were the empty elements, which completes the formation of source elements between the floating gate elements, produces unfinished word line elements;
• removing the sacrificial elements to the surface of said semiconductor region;
• forming word line element sidewall insulating spacers over the bare sidewalls of the unfinished word line elements, which finishes the word line elements;
• performing drain ion implantation through the now empty elements that are between word line elements to form drain regions that are self aligned to adjacent word line elements;
• forming drain pick up lines, containing drain contact regions contacting the drains that are self aligned to the drains and to the adjacent word line elements and drain lines contacting all drain contact regions of the same row.

A new method of fabricating a split gate flash memory device with multi-self-alignment having sharply tipped floating gates for efficient erasing, comprising:

• forming active regions, arranged in rows, disposed over a semiconductor region and separated by isolation regions, the active regions having had formed a gate insulating layer disposed over said semiconductor region and a first conductor layer disposed over said insulating layer;
• depositing a first insulating layer and patterning said first insulator layer into parallel strips disposed over said first conductor layer and running perpendicular to said rows;
• etching said first conductor layer to achieve a sloping top profile;
• depositing a floating gate insulator layer and performing CMP so that said floating gate insulator layer forms strips just filling the space between said strips of first insulator layer;
• removing successively, said strips of first insulator layer, said first conductor layer and said gate insulator layer from between said strips of floating gate insulator layer, and thus forming conductive floating gate layers having sharp edges for improved erasing efficiency, and thus forming structural elements that are referred to as unfinished floating gate elements and sacrificial elements that are denoted as F* and Y respectively, and which are identical except sacrificial elements are to be removed, and empty elements are denoted by X, and these structural elements are arranged in identical order along the rows of said active regions,as . . . YXF*XF*XYXF*XF*XY . . . so that empty elements fall between unfinished floating gate elements an both sides and between unfinished floating gate and sacrificial elements, sacrificial elements being the same in structure as unfinished floating gate elements except that they are to be removed, and where unfinished floating gate elements and sacrificial elements are created by forming a gate insulator layer over said semiconductor region and patterning said gate insulator layer to exist only in unfinished floating gate and sacrificial clement areas, forming floating gates conductive layers that are disposed over said gate insulator layer, and forming a floating gate insulator layer by depositing and patterning an insulator layer into parallel strips perpendicular to the row direction, so that the strips are disposed over corresponding unfinished floating gate elements and sacrificial elements;
• forming first a blanket conformal insulator layer and then a second conformal insulator layer within those empty elements that are between unfinished floating gate elements and extending over a portion of the adjacent unfinished floating gate elements, and performing spacer etching procedures on that portion of the blanket conformal insulator layer that is within those empty elements that are between unfinished floating gate elements and extending over a portion of the adjacent unfinished floating gate elements and on the second conformal insulator layer to form insulating spacers, which finishes the floating gate elements;
• performing a source ion implantation through the empty elements that are between floating gate elements and annealing to form source regions that are self aligned to adjacent floating gate elements and extend within said semiconductor region to under the adjoining floating gate regions;
• forming conductive source pick up lines, in those empty element that are between floating gate elements so that they are self aligned to the adjacent floating gate elements and to the source regions, and conductive word lines, in those empty elements that are between floating gate elements and sacrificial elements so that they are self aligned to the adjacent floating gate elements and adjacent sacrificial elements, by depositing a conductive layer and etching back so that the remaining conductive layer is well within what were the empty elements, and then forming a source element and word line element insulator layer to substantially fill what were the empty elements, which completes the formation of source elements between the floating gate elements, produces unfinished word line elements;
• removing the sacrificial elements to the surface of said semiconductor region;
• forming word line element sidewall insulating spacers over the bare sidewalls of the unfinished word line elements, which finishes the word line elements;
• performing drain ion implantation through the now empty elements that are between word line elements to form drain regions that are self aligned to adjacent word line elements;
• forming drain pick up lines, containing drain contact regions contacting the drains that are self aligned to the drains and to the adjacent word line elements and drain lines contacting all drain contact regions of the same row.