Back to results
US 2004/0166669 A1Published application
Method of manufacturing semiconductor device having dual damascene structure
AssigneeRenesas Technology Corp.
InventorTakayuki Saito
Life of this patent
Estimating the term…
Abstract
A via hole is formed so as to reach a Cu interconnection through an interlayer insulating film that covers the Cu interconnection. A conductive polymeric member is buried in the via hole by electrolysis. A resist pattern is formed on the interlayer insulating film by photolithography, and a trench is formed so as to be connected to the via hole by etching by using the resist pattern as a mask. The resist pattern and the conductive polymeric member are removed thereafter.
Claims6
A method of manufacturing a semiconductor device having a dual damascene structure, comprising the steps of:
- forming a via hole which reaches an underlying interconnection through an interlayer insulating film that covers the underlying interconnection;
- forming a conductive polymeric member in the via hole by electrolysis;
- forming a resist pattern on the interlayer insulating film after said step of forming a conductive polymeric member;
- and
- forming a trench connected to the via hole by etching by using the resist pattern as a mask.
2 more elements
Dependencies are inferred from the claim text.