Method for forming a SiGe heterojunction bipolar transistor having reduced base resistance

A method for forming a heterojunction bipolar transistor, comprising:

• forming a collector region in a semiconductor layer of a first conductivity type on a semiconductor substrate;
• forming an extrinsic base region in a polysilicon layer of the second conductivity type overlying the collector region;
• forming a dielectric layer over the extrinsic base region, wherein the dielectric layer and the extrinsic base region include a central aperture exposing a portion of the top surface of the collector region;
• forming an intrinsic base region in the central aperture, the intrinsic base region comprising a silicon germanium layer being selectively grown on an exposed top surface of the collector region and an exposed sidewall of the extrinsic base region in the center aperture;
• forming a spacer in a dielectric material over the intrinsic base region and along the sidewall of the dielectric layer;
• and
• forming an emitter region in a polysilicon layer of the first conductivity type, the emitter region overlying the dielectric layer and the spacer and being in electrical contact with the intrinsic base region.

A method for forming a heterojunction bipolar transistor, comprising:

• forming an epitaxial layer of a first conductivity type on a semiconductor substrate;
• forming a first dielectric layer on the epitaxial layer, the first dielectric layer including a first opening for exposing a portion of the top surface of the epitaxial layer;
• forming a first polysilicon layer of a second conductivity type on the first dielectric layer and the exposed epitaxial layer;
• forming a second dielectric layer on the first polysilicon layer, wherein the first polysilicon layer and the second dielectric layer include a second opening for exposing a portion of the top surface of the epitaxial layer, the second opening being smaller than the first opening;
• growing selectively a silicon germanium layer in the second opening, wherein the silicon germanium layer is grown on the top surface of the epitaxial layer and on the sidewall of the first polysilicon layer exposed by the second opening;
• forming a spacer along the sidewall of the silicon germanium layer and the sidewall of the second dielectric layer in the opening;
• and
• forming a second polysilicon layer of the first conductivity type over the second opening, wherein the second polysilicon layer overlies the second dielectric layer and the spacer and is in electrical contact with the silicon germanium layer.