Method of manufacturing high coupling ratio flash memory having sidewall spacer floating gate electrode

A method of manufacturing a flash memory, comprising the steps of:

• providing a substrate having a first gate structure and a second gate structure thereon, wherein the first gate structure and the second gate structure each has a dielectric layer, a first conductive layer and a cap layer;
• forming a tunneling oxide layer over the substrate and then forming first spacers on the sidewalls of the first conductive layer;
• forming a first conductive material layer over the substrate;
• forming a material layer over the first conductive material layer;
• forming a first patterned photoresist layer over the material layer, wherein the first patterned photoresist layer covers the area designated for forming a source region;
• removing the material layer and the first conductive material layer that are not covered by the first patterned photoresist layer by using the first patterned photoresist layer as a mask;
• removing the first patterned photoresist layer;
• performing an anisotropic etching process to remove a portion of the material layer and the first conductive material layer so as to form a second spacer and a second conductive layer;
• removing a portion of the second spacer;
• forming the source region in the substrate in the area between the first gate structure and the second gate structure;
• forming an inter-gate dielectric layer over the second conductive layer and then forming an insulating layer over the source region;
• forming a third conductive layer in the space between the first gate structure and the second gate structure;
• and
• forming a drain region in the substrate on the other side of the first gate structure and the second gate structure.