Method for increasing the Beta of PNP BJT device in CMOS process
AssigneeUnited Microelectronics Corp.
InventorTong-Hsin Lee
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Abstract
A method for improving the Beta (β) of a parasitic PNP bipolar junction transistor (BJT) in a conventional CMOS process includes the steps of: providing a P-type substrate having a shallow region corresponding to the P+ electrode of the parasitic PNP BJT and the P+ electrode is located within and in contact with an N-well; forming an electrostatic discharge (ESD) mask layer on the P-type substrate, wherein the mask layer has a pattern exposing an area corresponding to the P+ electrode of the PNP parasitic BJT, and exposing one electrode of an ESD device; and implanting P+ ions to the P-type substrate, thereby deepening a P/N junction of the P+ electrode of the parasitic BJT and the N-well.
Claims14
A method for increasing the Beta (β) of a parasitic bipolar junction transistor (BJT) in a CMOS, said method comprising:
- providing a substrate having an area corresponding to a first electrode of a parasitic BJT, a second electrode of said parasitic BJT being in contact between said first electrode and a third electrode of said parasitic BJT;
- forming a mask layer on said substrate, wherein said mask layer has a pattern exposing an area corresponding to said first electrode of said parasitic BJT;
- and
- implanting ions to said substrate, wherein implanted ions have the same conductivity type as said first electrode of said parasitic BJT, thereby deepening a junction of said first electrode and said second electrode of said parasitic BJT.
The method according to clam 1, further comprising another area, within said substrate, which corresponds to one electrode of an electrostatic discharge (ESD) device.
A method for increasing the Beta (β) of a parasitic PNP bipolar junction transistor (BJT) in a CMOS, said method comprising:
- providing a P-type substrate, wherein said P-type substrate includes a shallow region corresponding to a P+ electrode of a parasitic PNP BJT, said P+ electrode is located within and in contact with an N-well, thereby said P+ electrode, said N-well, and said P-type substrate forming said parasitic PNP BJT;
- forming an electrostatic discharge (ESD) mask layer on said P-type substrate, wherein said mask layer has a pattern exposing an area corresponding to said P+ electrode of said PNP parasitic BJT, and exposing one electrode of an ESD device;
- and
- implanting P+ ions to said P-type substrate, thereby deepening a P/N junction of said P+ electrode of said parasitic BJT and said N-well.
Dependencies are inferred from the claim text.