Substrate for the micro-lithography and process of manufacturing thereof
AssigneeSchott AG
InventorsLutz Aschke, Markus Schweizer, Jochen Alkemper, Axel Schindler, Frank Frost, Thomas Haensel, Renate Fechner
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Abstract
The invention relates to the manufacture of a substrate which is particularly suitable for EUV micro-lithography and comprises a base layer of low coefficient of thermal expansion (CTE) onto which at least one cover layer made of a semiconductor material is applied. Preferably, the cover layer is a silicon layer, preferably applied by ion beam sputtering. By an additional ion beam figuring treatment substrates of extremely accurate shape and extremely low roughness can be prepared.
Claims38
A process of manufacturing a substrate for a component used in EUV micro-lithography, comprising the following steps:
- providing a base layer consisting of a lithium-aluminosilicate glass ceramic having a coefficient of thermal expansion of no more than 0.1 ppm/K between 0° C. and 50° C.;
- polishing said base layer to a surface roughness of one nanometer rms at the most;
- applying a first cover layer consisting of silicon onto said base layer by ion beam sputtering up to a layer thickness between 20 nanometers and 200 nanometers;
- treating said first cover layer by a method selected from the group formed by ion beam figuring (IBF) and by magneto-rheologic polishing;
- applying a second cover layer comprising an organic lacquer up to a layer thickness between 20 and 200 nanometers;
- curing said second cover layer;
- at least partially removing said second cover layer by a method selected from the group formed by IBF and by magneto-rheologic polishing until a desired surface characteristic is reached.
A process of manufacturing a substrate for a component used in EUV micro-lithography, comprising the following steps:
- providing a base layer consisting of a lithium-aluminosilicate glass ceramic having a coefficient of thermal expansion of no more than 0.1 ppm/K between 0° C. and 50° C.;
- polishing said base layer to a surface roughness of one nanometer rms at the most;
- applying a first cover layer consisting of silicon onto said base layer by ion beam sputtering up to a layer thickness between 500 nanometers and 2000 nanometers;
- treating said first cover layer by a method selected from the group formed by IBF and by magneto-rheologic polishing, until a desired surface characteristic is reached.
A process of manufacturing a substrate, comprising the following steps:
- providing a base layer having a coefficient of thermal expansion of no more than 0.1 ppm/K;
- applying a first cover layer of a semiconductor material onto said base layer;
- and
- finishing said first cover layer until a desired surface characteristic is reached.
A substrate comprising a base layer and at least one cover layer, wherein said base layer consists of a material having a coefficient of thermal expansion of 0.1 ppm/K at the most, wherein said at least one cover layer consists of a semiconductor material, said substrate comprising a top surface having a shape precision of 50 nanometers PV at the most.
A substrate comprising a base layer and at least one cover layer, wherein said base layer consists of a material having a coefficient of thermal expansion of 0.1 ppm/K at the most, wherein said at least one cover layer consists of a semiconductor material, said substrate comprising a top surface having a surface roughness of 1 nanometer rms at the most.
Dependencies are inferred from the claim text.