System and method for inspecting errors on a wafer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChang-Cheng Hung, Hung-Chang Hsieh, Hsen-Lin Wu, Tyng-Hao Hsu
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Abstract
A method and system is disclosed for inspecting defects on a wafer. After acquiring at least one digitized image of at least one portion of a wafer, at least one design database file corresponding to the portion of the wafer is converted into at least one inspection file. After setting one or more error detection thresholds, the digitized image and the inspection file are compared by an inspection tool for detecting defects with regard to the portion of the wafer based on the set error detection thresholds.
Claims20
A method for inspecting defects in a wafer, the method comprising:
- acquiring at least one digitized image of at least one portion of a wafer;
- converting at least one design database file corresponding to the portion of the wafer into at least one inspection file;
- setting one or more error detection thresholds;
- and
- comparing the digitized image and the inspection file by an inspection tool for detecting defects with regard to the portion of the wafer based on the set error detection thresholds.
A method for inspecting mask patterning process induced defects in a wafer, the method comprising:
- acquiring at least one digitized image of at least one mask pattern on the wafer;
- converting at least one mask database file for a mask corresponding to the mask pattern into at least one inspection file specific to an inspection tool through an aerial image based processing;
- comparing the digitized image and the inspection file by the inspection tool;
- and
- detecting disallowed mask patterning process induced defects by examining differences.
A method for inspecting wafer processing induced defects for making a semiconductor device, the method comprising:
- acquiring at least one digitized image of at least one feature on the wafer;
- converting at least one design database file corresponding to the feature into at least one inspection file specific to an inspection tool through an aerial image based processing;
- comparing the digitized image and the inspection file by the inspection tool;
- and
- detecting disallowed wafer processing induced defects by examining differences between the inspection file and the digitized image corresponding to the feature.
A method for inspecting circuit layout related defects for making a semiconductor device, the method comprising:
- acquiring at least one digitized image of at least one feature on the wafer;
- converting at least one circuit design database file corresponding to the feature based on one circuit layout design into at least one inspection file through an aerial image based processing;
- comparing the digitized image and the inspection file by the inspection tool;
- and
- detecting disallowed circuit layout related defects by examining differences thereof.
Dependencies are inferred from the claim text.