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US 2004/0164417 A1Published application
Semiconductor device and manufacturing method thereof
AssigneeRenesas Technology Corp.
InventorsYasunori Yamashita, Kenichi Hatasako
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Abstract
Interfaces between an Al alloy layer and a Ti-containing layer are present in a through hole formed between a lower layer interconnection and an upper layer interconnection. In the interfaces, resistance element regions are formed through heat treatment. A resistance value between the lower layer interconnection and the upper layer interconnection can be adjusted by means of the resistance element region.
Claims12
A semiconductor device, comprising:
- a lower layer interconnection;
- an upper layer interconnection;
- an interlayer insulating film having a through hole formed between said lower layer interconnection and said upper layer interconnection;
- and
- a conductive layer provided in said through hole, and electrically connecting said lower layer interconnection to said upper layer interconnection;
- wherein
- an interface between an Al alloy layer and a Ti-containing layer is present in said through hole, and
- a resistance element region is provided in at least a portion of said interface.
5 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a lower layer interconnection;
- forming an interlayer insulating film on said lower layer interconnection, and forming a through hole in the interlayer insulating film;
- forming on a surface of said interlayer insulating film and inside the through hole, a conductive layer including a Ti-containing layer fabricated with at least one layer selected from a Ti layer, a TiN layer, and a TiW layer, and an Al alloy layer adjacent to said Ti-containing layer, fabricated with at least one layer selected from an AlSiCu layer, an AlSi layer and an AlCu layer;
- forming an upper layer interconnection by removing an unnecessary portion of said conductive layer;
- and
- subjecting said conductive layer in said through hole to heat treatment, to raise a resistance value between said lower layer interconnection and said upper layer interconnection.
3 more elements
Dependencies are inferred from the claim text.