Arrangement for ESD protection of an integrated circuit
AssigneeInfineon Technologies AG
InventorsAndrej Litwin, Ola Pettersson
Life of this patent
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Abstract
To protect a high-frequency integrated circuit (1) against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad (2), a semiconductor varistor (3) having low and essentially constant resistance for said normal operating voltages and higher resistance for said higher voltages is integrated between the bonding pad (2) and the input/output terminal together with the integrated circuit (1).
Claims12
An arrangement for protecting a high-frequency integrated circuit against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad, wherein the arrangement comprises a semiconductor varistor that is integrated between the bonding pad and the input/output terminal together with the integrated circuit and that has a low resistance for said normal operating voltages and a higher resistance for said higher voltages.
A protection arrangement comprising:
- a high-frequency integrated circuit comprising an input/output terminal and a bonding pad,
- a semiconductor varistor integrated between the bonding pad and the input/output terminal together with the integrated circuit which has a low resistance for a normal operating voltages and a higher resistance for higher voltages.
Dependencies are inferred from the claim text.