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US 2004/0164317 A1Published application
Heterojunction type compound semiconductor field effect transistor and its manufacturing method
AssigneeKabushiki Kaisha Toshiba
InventorsKazuya Nishihori, Masanori Ochi, Takao Noda, Yoshitomo Sagae, Kenji Hommyo
Life of this patent
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Abstract
A heterojunction type compound semiconductor field effect transistor includes a channel layer, a first electron supply layer, an electric field strength reducing layer, a first contact layer, a recess stopper layer, and a second contact layer sequentially stacked on a compound semiconductor substrate. This transistor has a double recess structure. The first contact layer is composed of GaAs or InGaAs doped with n type impurities with a high electron mobility. The electric field strength reducing layer is composed of intrinsic InGaP.
Claims20
A heterojunction type compound semiconductor field effect transistor comprising:
- a channel layer provided on a compound semiconductor substrate and composed of intrinsic GaAs or InGaAs;
- a first electron supply layer provided on the channel layer and composed of AlGaAs doped with n type impurities;
- an electric field strength reducing layer provided on the first electron supply layer and composed of intrinsic InGaP;
- a first contact layer provided on the electric field strength reducing layer and composed of GaAs or InGaAs doped with n type impurities;
- a recess stopper layer provided on the first contact layer and composed of intrinsic InGaP;
- a second contact layer provided on the recess stopper layer and composed of GaAs doped with n type impurities of a concentration higher than that of the first contact layer;
- a wide recess opening formed to penetrate the second contact layer so as to expose a surface of the recess stopper layer;
- a narrow recess opening formed in the wide recess opening to penetrate the recess stopper layer, the first contact layer, and the electric field strength reducing layer so as to expose a surface of the first electron supply layer;
- a gate electrode provided on the surface of the first electron supply layer exposed from a bottom of the narrow recess opening;
- and
- a source electrode and a drain electrode provided on the second contact layer outside the wide recess opening so that the wide recess opening is sandwiched between the source electrode and the drain electrode.
8 more elements
A heterojunction type compound semiconductor field effect transistor comprising:
- a channel layer provided on a compound semiconductor substrate and composed of intrinsic GaAs or InGaAs;
- a first electron supply layer provided on the channel layer and composed of AlGaAs doped with n type impurities;
- an electric field strength reducing layer provided on the first electron supply layer and composed of intrinsic InGaP;
- a first contact layer provided on the electric field strength reducing layer and composed of GaAs or InGaAs doped with n type impurities;
- a recess stopper layer provided on the first contact layer and composed of intrinsic InGaP;
- a second contact layer provided on the recess stopper layer and composed of GaAs doped with n type impurities of a concentration higher than that of the first contact layer;
- a wide recess opening formed to penetrate the second contact layer and the recess stopper layer so as to expose a surface of the first contact layer;
- a narrow recess opening formed in the wide recess opening to penetrate the first contact layer and the electric field strength reducing layer so as to expose a surface of the first electron supply layer;
- a gate electrode provided on the surface of the first electron supply layer exposed from a bottom of the narrow recess opening;
- and
- a source electrode and a drain electrode provided on the second contact layer outside the wide recess opening so that the wide recess opening is sandwiched between the source electrode and the drain electrode.
8 more elements
A heterojunction type compound semiconductor field effect transistor comprising:
- a channel layer provided on a compound semiconductor substrate and composed of intrinsic GaAs or InGaAs;
- a first electron supply layer provided on the channel layer and composed of AlGaAs doped with n type impurities;
- an electric field strength reducing layer provided on the first electron supply layer and composed of intrinsic InGaP;
- a first contact layer provided on the electric field strength reducing layer and composed of GaAs or InGaAs doped with n type impurities;
- a recess stopper layer provided on the first contact layer and composed of intrinsic InGaP;
- a second contact layer provided on the recess stopper layer and composed of GaAs doped with n type impurities of a concentration higher than that of the first contact layer;
- a wide recess opening formed to penetrate the second contact layer so as to expose a surface of the recess stopper layer;
- a narrow recess opening formed in the wide recess opening to penetrate the recess stopper layer and the first contact layer so as to expose a surface of the electric field strength reducing layer;
- a gate electrode provided on the surface of the electric field strength reducing layer exposed from a bottom of the narrow recess opening;
- and
- a source electrode and a drain electrode provided on the second contact layer outside the wide recess opening so that the wide recess opening is sandwiched between the source electrode and the drain electrode.
8 more elements
A heterojunction type compound semiconductor field effect transistor comprising:
- a channel layer provided on a compound semiconductor substrate and composed of intrinsic GaAs or InGaAs;
- a first electron supply layer provided on the channel layer and composed of AlGaAs doped with n type impurities;
- an electric field strength reducing layer provided on the first electron supply layer and composed of intrinsic InGaP;
- a first contact layer provided on the electric field strength reducing layer and composed of GaAs or InGaAs doped with n type impurities;
- a recess stopper layer provided on the first contact layer and composed of intrinsic InGaP;
- a second contact layer provided on the recess stopper layer and composed of GaAs doped with n type impurities of a concentration higher than that of the first contact layer;
- a wide recess opening formed to penetrate the second contact layer and the recess stopper layer so as to expose a surface of the first contact layer;
- a narrow recess opening formed in the wide recess opening to penetrate the first contact layer so as to expose a surface of the electric field strength reducing layer;
- a gate electrode provided on the surface of the electric field strength reducing layer exposed from a bottom of the narrow recess opening;
- and
- a source electrode and a drain electrode provided on the second contact layer outside the wide recess opening so that the wide recess opening is sandwiched between the source electrode and the drain electrode.
8 more elements
A manufacturing method for a heterojunction type compound semiconductor field effect transistor, the method comprising:
- forming a channel layer composed of intrinsic GaAs or InGaAs on a compound semiconductor substrate;
- forming a first electron supply layer composed of AlGaAs on the channel layer;
- forming an electric field strength reducing layer composed of intrinsic InGaP on the electron supply layer;
- forming a first contact layer composed of GaAs or InGaAs doped with n type impurities, on the electric field strength reducing layer;
- forming a recess stopper layer composed of intrinsic InGaP, on the first contact layer;
- forming, on the recess stopper layer, a second contact layer composed of GaAs doped with n type impurities of a concentration higher than that of the first contact layer;
- wet-etching the second contact layer to form a wide recess opening penetrating the second contact layer using the recess stopper layer as a stopper;
- forming a source electrode and a drain electrode on the second contact layer outside the wide recess opening so that the wide recess opening is sandwiched between the source electrode and the drain electrode;
- wet-etching the first contact layer in the wide recess opening using the electric field strength reducing layer as a stopper;
- wet-etching the electric field strength reducing layer in the wide recess opening to form a narrow recess opening penetrating the recess stopper layer, the first contact layer, and the electric field strength reducing layer using the first electron supply layer as a stopper;
- and
- forming a gate electrode on a surface of the first electron supply layer exposed from a bottom of the narrow recess opening.
9 more elements
A manufacturing method for a heterojunction type compound semiconductor field effect transistor, the method comprising:
- forming a channel layer composed of intrinsic GaAs or InGaAs on a compound semiconductor substrate;
- forming a first electron supply layer composed of AlGaAs on the channel layer;
- forming an electric field strength reducing layer composed of intrinsic InGaP on the electron supply layer;
- forming a first contact layer composed of GaAs or InGaAs doped with n type impurities, on the electric field strength reducing layer;
- forming a recess stopper layer composed of intrinsic InGaP, on the first contact layer;
- forming, on the recess stopper layer, a second contact layer composed of GaAs doped with n type impurities of a concentration higher than that of the first contact layer;
- wet-etching the second contact layer using the recess stopper layer as a stopper;
- wet-etching the recess stopper layer to form a wide recess opening penetrating the second contact layer and the recess stopper layer using the first contact layer as a stopper;
- forming a source electrode and a drain electrode on the second contact layer outside the wide recess opening so that the wide recess opening is sandwiched between the source electrode and the drain electrode;
- wet-etching the first contact layer in the wide recess opening using the electric field strength reducing layer as a stopper;
- wet-etching the electric field strength reducing layer in the wide recess opening to form a narrow recess opening penetrating the first contact layer and the electric field strength reducing layer using the first electron supply layer as a stopper;
- and
- forming a gate electrode on a surface of the electron supply layer exposed from a bottom of the narrow recess opening.
10 more elements
A manufacturing method for a heterojunction type compound semiconductor field effect transistor, the method comprising:
- forming a channel layer composed of intrinsic GaAs or InGaAs on a compound semiconductor substrate;
- forming a electron supply layer composed of AlGaAs on the channel layer;
- forming an electric field strength reducing layer composed of intrinsic InGaP on the first electron supply layer;
- forming a first contact layer composed of GaAs or InGaAs doped with n type impurities, on the electric field strength reducing layer;
- forming a recess stopper layer composed of intrinsic InGaP, on the first contact layer;
- forming, on the recess stopper layer, a second contact layer composed of GaAs doped with n type impurities of a concentration higher than that of the first contact layer;
- wet-etching the second contact layer to form a wide recess opening penetrating the second contact layer using the recess stopper layer as a stopper;
- forming a source electrode and a drain electrode on the second contact layer outside the wide recess opening so that the wide recess opening is sandwiched between the source electrode and the drain electrode;
- wet-etching the recess stopper layer in the wide recess opening using the first contact layer as a stopper;
- wet-etching the first contact layer in the wide recess opening to form a narrow recess opening penetrating the recess stopper layer and the first contact layer using the electric field strength reducing layer as a stopper;
- and
- forming a gate electrode on a surface of the electric field strength reducing layer exposed from a bottom of the narrow recess opening.
9 more elements
A manufacturing method for a heterojunction type compound semiconductor field effect transistor, the method comprising:
- forming a channel layer composed of intrinsic GaAs or InGaAs on a compound semiconductor substrate;
- forming a first electron supply layer composed of AlGaAs on the channel layer;
- forming an electric field strength reducing layer composed of intrinsic InGaP on the electron supply layer;
- forming a first contact layer composed of GaAs or InGaAs doped with n type impurities, on the electric field strength reducing layer;
- forming a recess stopper layer composed of intrinsic InGaP, on the first contact layer;
- forming, on the recess stopper layer, a second contact layer composed of GaAs doped with n type impurities of a concentration higher than that of the first contact layer;
- wet-etching the second contact layer using the recess stopper layer as a stopper;
- wet-etching the recess stopper layer to form a wide recess opening penetrating the second contact layer and the recess stopper layer using the first contact layer as a stopper;
- forming a source electrode and a drain electrode on the second contact layer outside the wide recess opening so that the wide recess opening is sandwiched between the source electrode and the drain electrode;
- wet-etching the first contact layer in the wide recess opening to form a narrow recess opening penetrating the first contact layer using the electric field strength reducing layer as a stopper;
- and
- forming a gate electrode on a surface of the electric field strength reducing layer exposed from a bottom of the narrow recess opening.
9 more elements
Dependencies are inferred from the claim text.