Clock provisioning techniques

A system comprising:

• a serializer device comprising a multiplexer to convert an input signal format from parallel to serial format based upon a reference clock signal and further comprising a signal gate to selectively transfer a first or second clock signal, wherein the multiplexer and signal gate are formed substantially within the same die and wherein the reference clock signal is based on the transferred signal;
• a de-serializer device comprising a clock source to provide the first clock signal and further comprising a de-multiplexer to convert serial format signals to parallel format;
• a layer 2 processor to provide parallel format data signals to the serializer device and receive parallel data signals from the de-serializer device;
• and
• an interface device to receive and transfer information with the layer 2 processor.