Apparatus for processing wafers

A wafer processing apparatus, comprising:

• a first wafer transporter;
• a process station coupled to said first wafer transporter, said process station including:
• a first plurality of wafer processing stacks, each of said plurality of wafer processing stacks including a plurality of wafer processing modules, and
• a second wafer transporter coupled to said plurality of wafer processing modules, each of said plurality of wafer processing modules adjacent, and accessible by, said second wafer transporter;
• and
• a third wafer transporter coupled to said process station,
• wherein any of said plurality of wafer processing modules in any of said plurality of wafer processing stacks can be accessed by at least two adjacent wafer transporters selected from the group consisting of said first wafer transporter, said second wafer transporter, and said third wafer transporter.

A wafer processing apparatus, comprising:

• a first wafer transporter;
• a first process station coupled to said first wafer transporter, said first process station including:
• a first plurality of wafer processing stacks, each of said first plurality of wafer processing stacks including a first plurality of wafer processing modules, and
• a second wafer transporter coupled to said first plurality of wafer processing stacks, each of said first plurality of wafer processing modules adjacent, and accessible by, said second wafer transporter;
• a second process station coupled to said first wafer transporter, said second process station including:
• a second plurality of wafer processing stacks, each of said second plurality of wafer processing stacks including a second plurality of wafer processing modules, and
• a third wafer transporter coupled to said plurality of wafer processing stacks, each of said second plurality of wafer processing modules adjacent, and accessible by, said third wafer transporter;
• and
• a fourth wafer transporter coupled to both said first process station and said second process station,
• wherein each of said first process station and said second process station are individually symmetrical with regard to wafer transporter access on both an X axis and a Y axis.