Integrated process flow to improve copper filling in a damascene structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYun Hung Shen
Life of this patent
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Abstract
An improved and new process for fabricating a dual damascene structure of copper has been developed. Conventional methods use silicon nitride as a protective liner of the dual damascene trench/via. However, problems arise with the conventional methods due to recessed nitride at the damascene bottom via area, which affects the performance of the subsequent copper fill, and makes for a noncontinuous barrier coating at the bottom of the via. This improved and new process uses a thin nitride spacer, approximately 100 Angstroms thick, at the bottom of the via, thus preventing recessed nitride during the resist stripping process.
Claims27
A method for fabricating a nitride spacer, in dual damascene processing, the method comprising:
- providing an insulating layer overlying a semiconductor substrate;
- providing a patterned metal wiring layer over said insulating layer;
- depositing a first passivating layer over said metal wiring layer;
- depositing a first low dielectric constant layer over said first passivating layer;
- depositing a second passivating layer over said second low dielectric constant layer;
- forming via and trench openings in said first and second low dielectric constant layers;
- blanket depositing by plasma enhanced chemical vapor deposited, a SiN conformal layer over said via and trench openings;
- etching back of said SiN conformal layer causing a small portion of the SiN layer to remain near the bottom of said via opening, and exposing a portion of the first passivating layer, thus a plasma enhanced SiN spacer is formed at the bottom of the via opening.
A method in dual damascene processing, for fabrication of trench and via openings, the method comprising:
- providing an insulating layer overlying a semiconductor substrate;
- providing a patterned metal wiring layer over said insulating layer;
- depositing a first passivating layer over said metal wiring layer;
- depositing a first low dielectric constant layer over said first passivating layer;
- depositing a second passivating layer over said second low dielectric constant layer;
- forming via and trench openings in said first and second low dielectric constant layers;
- blanket depositing by plasma enhanced chemical vapor deposited, a SiN conformal layer over said via and trench openings;
- etching back of said SiN conformal layer forming a plasma enhanced SiN spacer at the bottom of the via opening and exposing a portion of the first passivating layer;
- providing patterned photoresist to expose the SiN spacer at the bottom of the via and expose a portion of the first passivating layer;
- removal of the SiN spacer at the bottom of the via, and the exposed portion of the first passivation layer, thus forming properly shaped trench and via openings in dual damascene.
A method in dual damascene processing, for fabrication inlaid copper interconnect wiring and contact vias, the method comprising:
- (a) providing an insulating layer overlying a semiconductor substrate;
- (b) providing a patterned metal wiring layer over said insulating layer;
- (c) depositing a first passivating layer over said metal wiring layer;
- (d) depositing a first low dielectric constant layer over said first passivating layer;
- (e) depositing a second passivating layer over said second low dielectric constant layer;
- (f) forming via and trench openings in said first and second low dielectric constant layers;
- (g) blanket depositing by plasma enhanced chemical vapor deposited, a SiN conformal layer over said via and trench openings;
- (h) etching back of said SiN conformal layer forming a plasma enhanced SiN spacer at the bottom of the via opening and exposing a portion of the first passivating layer;
- (i) providing patterned photoresist to expose the SiN spacer at the bottom of the via and expose a portion of the first passivating layer;
- (j) removal of the SiN spacer at the bottom of the via, and the exposed portion of the first passivation layer, to complete the formation of trench and via openings in a dual damascene process;
- (k) forming a barrier and copper seed layer in said trench and via openings;
- (1) plating copper on said copper seed layer, filling trench and via openings with excess copper, then annealing;
- (m) removing said excess copper and planarizing back the excess copper by chemical mechanical polishing, thus completing the fabrication of inlaid copper interconnect wiring and contact vias.
Dependencies are inferred from the claim text.