High coupling split-gate transistor

A method of forming split-gate transistors, comprising the steps of:

• providing a substrate which has a plurality of isolation bars formed therein;
• forming a tunneling oxide layer on the substrate between the isolation bars;
• forming a first polysilicon layer on the tunneling oxide layer;
• forming a plurality of nitride spacers, wherein each spacer is formed over one of the isolation bars, and wherein the plurality of spacers divides the first polysilicon layer into a plurality of U-shaped floating gates;
• forming a plurality of polysilicon spacers on the nitride spacers;
• removing the plurality of nitride spacers;
• forming a dielectric layer on the floating gates;
• and
• forming a second polysilicon layer on the dielectric layer, wherein the plurality of spacers divides the second polysilicon layer into a plurality of U-shaped control gates.

A method of forming split-gate transistors, comprising the steps of:

• forming a first polysilicon layer on a substrate which has a plurality of isolation bars formed therein;
• forming a plurality of trenches in the first polysilicon layer, wherein each trench is formed over one of the isolation bars in a direction parallel to the bars;
• forming a plurality of nitride spacers by filling the plurality of trenches with itride, wherein the plurality of spacers divides the first polysilicon layer into a plurality f U-shaped floating gates;
• forming a plurality of polysilicon spacers on the nitride spacers;
• removing the plurality of nitride spacers;
• forming a dielectric layer on the floating gates;
• and
• forming a second polysilicon layer on the dielectric layer, wherein the plurality of spacers divides the second polysilicon layer into a plurality of U-shaped control gates.