Loading patent…
AssigneeInternational Business Machines Corporation
InventorsChing-Te K. Chuang, Rajiv V. Joshi, Michael G. Rosenfield
Estimating the term…
An integrated circuit that may include an array such as a static random access memory (SRAM) with high threshold device array devices and in selected other devices to reduce leakage. Devices with high threshold have a thicker gate oxide or a high k dielectric gate oxide that is selected based on threshold voltage (VT) variations with gate oxide dielectric type or gate oxide thickness for the particular technology, e.g., PD SOI CMOS. High threshold devices may be used in non-core circuits, e.g., test circuits. Also, non-critical paths may be identified and a non-critical path margin identified. A thicker device threshold is selected for non-critcal path FETs based on the non-critical path margin. Non-critical path delays are re-checked. FETs are formed with the selected thicker gate oxide for any non-critical paths passing the re-check and in array FETs with non-selected FETs being formed with normal gate oxide thickness.
An integrated circuit (IC) chip including comprising:
A static random access memory (SRAM) including an array of SRAM cells, each of said SRAM cells comprising:
A (CMOS) static random access for memory (SRAM), selected field effect transistors (FETs) having a design threshold voltage (VT+) different than a stated design threshold voltage (VT), said SRAM including an SRAM array comprising:
A circuit design method for minimizing circuit leakage, said method comprising the steps of:
Dependencies are inferred from the claim text.