Via programmable gate array interconnect architecture
AssigneeLeopard Logic, Inc.
InventorsDieter Spaderna, Dale Wong
Life of this patent
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Abstract
A segmentation architecture for wiring segments which provides interconnections for a gate array integrated circuit is described. Programming is provided by selectable vias between wiring segments and to the semiconductor substrate surface. The wiring segments of two interconnection layers are arranged in two directions and a programmable buffer can drive signals in a selectable direction depending upon how the via contacts are made to the buffer by the wiring segments carrying the buffer signals.
Claims17
A programmable gate array having functionality for an application determined by vias defined by at least one via layer mask, said programmable gate array comprising
- a first interconnection layer having a plurality of wiring segments aligned in a plurality of tracks in a first direction and in a second direction orthogonal to said first direction,
- a second interconnection layer displaced from said first interconnection layer in a vertical direction orthogonal to said first and second directions, said second interconnection layer having a plurality of wiring segments aligned in said tracks with respect to said plurality of wiring segments of said first interconnection layer so that each end of wiring segments of said first interconnection layer is displaced in said vertical direction from an end of wiring segments of said second interconnection layer;
- and
- vias defined by said via layer mask providing interconnections between selected ends of said wiring segments in said first and second interconnection layers.
A programmable gate array having functionality for an application determined by vias defined by at least one via layer mask, said programmable gate array comprising
- a first interconnection layer having a plurality of wiring segments aligned in a plurality of tracks in a first direction and in a second direction orthogonal to said first direction,
- a second interconnection layer displaced from said first interconnection layer in a vertical direction orthogonal to said first and second directions, said second interconnection layer having a plurality of wiring segments aligned with respect to said plurality of wiring segments of said first interconnection layer including single wiring segments in said second interconnection layer each having portions displaced in said vertical direction from contiguous wiring segments of said first interconnection layer in the same track;
- and
- vias defined by said via layer mask providing interconnections between contiguous wiring segments in said first interconnection layer in the same track and portions of said single wiring segments in said second interconnection layer whereby said contiguous wiring segments in said first interconnection layer in the same track are interconnected.
Dependencies are inferred from the claim text.