Scheme for eliminating the channel unexpected turn-on during ESD zapping

Abstract

This invention provides a circuit for eliminating unexpected transistor channel turn-on caused by electrostatic discharge, ESD, zapping. It provides circuits which detect ESD over-voltage conditions and which pull down the voltage to the sensitive logic devices in the input/output pre-driver circuitry during ESD zapping. There is an Input/Output control circuit which interfaces with the sense circuit, feedback circuit and with the input/output pad of the semiconductor chip to be protected from ESD damage. The purpose of this I/O circuit is to use the ESD sense circuit and an internal feedback node to pull down the voltage on the gates of the MOSFET devices most vulnerable to unexpected channel turn on during the during of the ESD over-voltage condition.

Dependencies are inferred from the claim text.