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US 2004/0104491 A1Published application
Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive
OwnerMichael E. Connell, Tongbi Jianginventors
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Abstract
A method and apparatus for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped. The SBL may also serve as, or support, an adhesive layer for die attach and be of a markable material for an enhanced marking method.
Claims24
A semiconductor die, comprising:
- a semiconductor substrate having a front side and a back side;
- an integrated circuit on a portion of said front side;
- a passivation layer covering a portion of said integrated circuit;
- and
- a stress-balancing layer covering at least a portion of said back side.
2 more elements
A nonwarp semiconductor die, comprising:
- a semiconductor substrate having a front side, a back side, and a low ratio of height to a horizontal dimension;
- an integrated circuit on said front side;
- a passivation layer covering a portion of said integrated circuit exerting a stress on said substrate front side;
- and
- a stress-balancing layer covering at least a portion of said back side, said stress-balancing layer for balancing a portion of said front side stress with a generally equivalent back side stress.
2 more elements
A semiconductor die, comprising:
- a semiconductor substrate having a front side having an integrated circuit on a portion thereof and a back side;
- a passivation layer covering a portion of said integrated circuit;
- and
- a stress-balancing layer covering at least a portion of said back side.
1 more element
A reduced stress semiconductor die, comprising:
- a semiconductor substrate having a front side, a back side, and a low ratio of the height of the semiconductor substrate to a horizontal dimension of the semiconductor substrate;
- an integrated circuit on said front side of the semiconductor substrate;
- a passivation layer covering a portion of said integrated circuit causing a force acting on a portion of said substrate front side;
- and
- a force-balancing layer covering at least a portion of said back side, said force-balancing layer for balancing a portion of said force on said front side.
2 more elements
Dependencies are inferred from the claim text.