US 2004/0104437 A1 · Arrangement and method for ESD protection

Abstract

An arrangement (200) and method for scalable ESD protection of a semiconductor structure (140), a protection structure (120) providing a discharge transistor (110) path from an input/output node (130) to ground or another node if a threshold voltage is reached, wherein the discharge transistor is a self-triggered transistor having collector/drain (220) and emitter/source (210) regions, and a base/bulk region (260) having one or more floating regions (240) between the collector/drain (220) and emitter/source (210) regions. The floating region (N or P) modulates the threshold voltage Vt1 for ESD protection. Vt1 can be adjusted by shifting the floating region location. Splitting of the electric field into two parts reduces the maximum of the electric field. Vt1 can be adjusted volt-by-volt to suit application needs. ESD capability is increased by better current distribution in the silicon. This provides the advantages of reduced die size, faster time-to-market, less redesign cost, and better ESD performance.

Claims22

Dependent claims

A voltage protection arrangement for use to protect a semiconductor structure from electro-static discharge voltage at an input node thereof, the arrangement comprising:

discharge means, having an input for coupling to the input node, and an output for coupling to ground, the discharge means being arranged to provide a discharge path from the input node to ground if the voltage at the input node exceeds a threshold voltage,
wherein the discharge means comprises self-triggered transistor means having one of:
collector and emitter regions if said self-triggered transistor means comprises bipolar transistor means, and
drain and source regions if said self-triggered transistor means comprises MOS transistor means, and
at least one floating region therein arranged to modify a threshold voltage by separating an electric field between one of:
the collector and emitter regions when the self-triggered transistor means comprises bipolar transistor means, and
the drain and source regions when the self-triggered transistor means comprises MOS transistor means.

4 more elements

A method of voltage protection for use to protect a semiconductor structure from electro-static discharge voltage at an input node thereof, the method comprising:

providing discharge means, having an input coupled to the input node, and an output coupled to ground, the discharge means providing a discharge path from the input node to ground if the voltage at the input node exceeds a threshold voltage,
wherein the discharge means comprises self-triggered transistor means having one of:
collector and emitter regions if said self-triggered transistor means comprises bipolar transistor means, and
drain and source regions if said self-triggered transistor means comprises MOS transistor means, and
at least one floating region therein arranged to modify a threshold voltage by separating an electric field between one of:
the collector and emitter regions when the self-triggered transistor means comprises bipolar transistor means, and
the drain and source regions when the self-triggered transistor means comprises MOS transistor means.

4 more elements

Dependencies are inferred from the claim text.

Arrangement and method for ESD protection

Life of this patent

Arrangement and method for ESD protection

Life of this patent

Abstract

Claims22