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US 2004/0104432 A1Published application
Semiconductor device having fully and partially depleted SOI elements on a substrate
AssigneeOki Electric Industry Co., Ltd.
InventorMarie Hiraizumi
Life of this patent
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Abstract
A semiconductor device includes a silicon layer on an insulating layer. The silicon layer has a first area and a second area. The FD-MOSFET is formed in the first area and the PD-MOSFET formed in the second area. The semiconductor device of the present invention satisfies the. following formulas; the thickness of the silicon layer is 28 nm to 42 nm, the impurity concentration Df cm−3 of the first area is Df≦9.29* 1015* (62.46−ts) and Df≦2.64 * 1015*(128.35−ts), the impurity concentration Dp of the second area is Dp≦9.29 * 1015*(62.46−ts) and Dp≦2.64*1015* (129.78−ts).
Claims6
A semiconductor device comprising:
- a substrate having an insulating layer formed thereon;
- a silicon layer having a thickness ts formed on the insulating layer, the silicon layer including a first area having a first impurity concentration of Df cm−3, and a second area having a second condition of Dp cm−3;
- a fully-depleted MOSFET formed in the first area of the silicon substrate;
- and
- a partially-depleted MOSFET formed in the second area of the silicon layer;
- wherein the semiconductor device satisfies the following condition:
- 28 nm≦ts ≦42nm
- Df≦9.29*1015*(62.46−ts)
- Df≦2.64*1015*(128.35−ts)
- Dp≧9.29*1015*(62.46−ts) Dp≧2.64*1015*(129.78−ts).
7 more elements
Dependencies are inferred from the claim text.