Instruction processor systems and methods

A method of generating configuration information and associated executable code based on a customisation specification, which includes application information including application source code and customisation information including design constraints, for implementing an instruction processor using re-programmable hardware, the method comprising the steps of:

• generating a template for each processor style identified as a candidate for implementation;
• analysing instruction information for each template and determining instruction optimisations;
• compiling the application source code to include the instruction optimisations and generate executable code;
• analysing architecture information for each template and determining architecture optimisations;
• generating configuration information including the architecture optimisations;
• and
• generating device-specific configuration information from the configuration information including the architecture optimisations.

A management system for managing run-time re-configuration of an instruction processor implemented using re-programmable hardware, comprising:

• a configuration library containing configuration information for a plurality of instruction processor implementations;
• a code library for containing associated executable code for the implementations;
• a loader for loading application data and, as required, configuration information and associated executable code into re-programmable hardware for implementation and execution of an instruction processor;
• a loader controller for signalling the loader to load application data and, as required, configuration information and associated executable code, and execute the executable code;
• a run-time monitor for obtaining run-time statistics relating to operation of the instruction processor;
• an optimisation determiner configured to receive the run-time statistics, and being operable to instruct the loader to load new configuration information and associated executable code for a new implementation into the re-programmable hardware;
• and
• an optimisation instructor for invoking the optimisation determiner.

A method of managing run-time re-configuration of an instruction processor implemented in re-programmable hardware, comprising the steps of:

• providing a configuration library containing configuration information for a plurality of instruction processor implementations;
• providing a code library for containing associated executable code for the implementations;
• loading application data and, as required, configuration information and executable code into re-programmable hardware for implementation and execution of an instruction processor;
• executing the executable code;
• obtaining run-time statistics relating to operation of the instruction processor;
• and
• loading new configuration information and associated executable code for a new implementation into the re-programmable hardware.